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FX589 Datasheet, PDF (4/18 Pages) CML Microcircuits – Low-Voltage/High-Speed GMSK Modem
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Application Information
VDD
XTAL
1
C3
X1
XTAL
R2
XTAL/CLOCK
C2
V SS
2
XTAL/CLOCK
ClkDivA
ClkDivB
Rx HOLD
RxDCacq
PLLacq
Rx PS
V BIAS
R4
Rx FEEDBACK
R3
Rx SIGNAL IN
C6
VSS
C5
1
24
2
23
3
22
4
21
5
20
6 FX589P 19
7
18
8
17
9
16
10
15
11
14
12
13
VDD
Rx S/N
Tx CLOCK
Rx CLOCK
Rx DATA
Tx DATA
Tx PS
Tx ENABLE
Tx OUT
R1
BT
Doc2
Doc1
C4
V SS
C7
C8
C1
V SS
External Components
Component
Value Tolerance
R1
Note 1
±5%
R
2
1.0MΩ
±10%
R
Note 2
±10%
3
R
4
100kΩ
±10%
C
Note 1
±10%
1
C
Note 5
2
Fig.2 Recommended External Components
C3
Note 5
C4
100nF
±20%
C5
1.0µF
±20%
C6
22.0pF
±20%
C7
Note 4
C8
Note 4
X1
Note 3
Notes
1. The RC network formed by R1 and C1 is required
between the Tx Out pin and the input to the
modulator. This network, which can form part of any
dc level shifting and gain adjustment circuitry, forms
an important part of the transmit signal filtering.
The ground connection to the capacitor C1 should be
positioned to give maximum attenuation of high-
frequency noise into the modulator.
The component values should be chosen so that the
product of the resistance (Ohms) and the capacitance
(Farads) is: BT of 0.3 = 0.34/bit rate (bits/second)
BT of 0.5 = 0.22/bit rate (bits/second).
Data Rate
BT = 0.3
(b/s)
R1 (kΩ) C1 (pF)
4000
120
680
4800
100
680
8000
91
470
9600
91
390
16000
47
470
19200
100
180
32000
47
220
38400*
47
180
64000*
56
100
* VDD >= 4.5V
BT = 0.5
R1 (kΩ) C1 (pF)
120
470
100
470
120
220
47
470
91
150
91
120
47
150
47
120
51
68
Note that in all cases, the value of R1 should be not less
than
47.0kΩ
and
that
the
calculated
value
of
C
1
includes
calculated parasitic (circuit) capacitances.
2. R3, R4 and C6 form the gain components for the Rx
Input signal. R3 should be chosen as required by the
signal input level.
3. The FX589 can operate correctly with Xtal/Clock
frequencies of 1.0MHz to 8.2MHz (VDD = 5.0V) and
1.0MHz to 5.0MHz (V = 3.0V); see Table 1 for
DD
examples. Operation of this device without a Xtal or
Clock input may cause device damage.
4. C7 and C8 should both be 15.0nF for a data rate of
8kb/s, and inversely proportional to the data rate for
other data rates, e.g. 30.0nF at 4kb/s, 1.8nF at
64kb/s.
5. The value chosen for C2 and C3 (including stray
capacitances) should be suitable for the applied VDD
and the frequency of X1.
As a guide: C2 = C3 = 33.0pF at 1.0MHz falling to
18pF at the maximum frequency.
At 3 volts, C2 = C3 = 33.0pF falling to 18pF at 5.0MHz.
The equivalent series resistance of X1 should be less
than 2.0kΩ falling to 150Ω at the maximum frequency.
Stray capacitance on the Xtal/clock circuit pins must
be minimised.
4
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