FX589 Datasheet, PDF (5/18 Pages) CML Microcircuits – Low-Voltage/High-Speed GMSK Modem

Application Information ......
Rx FREQUENCY
DISCRIMINATOR
SIGNAL AND
DC LEVEL
ADJUSTMENT
Rx SIGNAL IN
Rx FEEDBACK
RxD
µCONTROLLER ^RxC
or UART ^TxD
TxC
Rx DATA
Rx CLOCK
Tx DATA
Tx CLOCK
Rx
CIRCUITS
Tx
CIRCUITS
FX589
GMSK MODEM
Fig.3 External Signal Paths
FREQUENCY
MODULATOR
SIGNAL AND
DC LEVEL
ADJUSTMENT
Tx OUT
Clock Oscillator and Dividers
The Tx and (nominal) Rx data rates are determined
by division of the frequency present at the Xtal pin,
which may be generated by the on-chip Xtal oscillator
or be derived from an external source. Any Xtal/clock
frequency in the range 1.0MHz to 5.0MHz (V = 3.0V)
DD
or 1.0MHz to 8.2MHz (V_DD = 5.0V) may be employed,
depending upon the desired data rate.
A division ratio to facilitate data-rate setting is
controlled by the logic level inputs on the ClkDivA/B
pins, and is shown in Table 1 (below) - together with
examples of how various ‘standard’ data-rates may be
derived from common µP or Xtal frequencies.
Data Rate = Xtal/Clock Frequency
Division Ratio (ClkDivA/B)
Note the device operation is not guaranteed
above 64,000 bits/s or below 4,000 bits/s at
the relevant supply voltage
8.192
Xtal/Clock Frequency (MHz)
4.9152
4.096
[12.288/3]
2.4576
[12.288/5]
2.048
[6.144/3]
Inputs
Division Ratio:
ClkDiv ClkDiv
Xtal Freq
A
B
Data Rate
0
0
128
0
1
256
1
0
512
1
1
1024
Table 1 Clock/Data Rates
64000*
32000
16000
8000
Data Rate (b/s)
38400*
19200
9600
4800
32000
16000
8000
4000
19200
9600
4800
16000
8000
4000
* V >= 4.5V
DD
Fig.4 Minimum µController System Connections
5