CMX991 Datasheet, PDF (54/56 Pages) CML Microcircuits – Two-mode demodulator

RF Quadrature Transceiver / RF Quadrature Receiver
CMX991/CMX992
8.1.3.4 AC Parameters – IF LO Integer N PLL
Phase Locked Loop
Supply Current (Enabled)
Supply Current (Standby)
Reference Input
Frequency
Level
Divide Ratios (M divider)
IF Synthesiser
Comparison Frequency
Input Frequency Range
Input Level
Divide Ratios (N divider)
Charge Pump Current
1Hz Normalised SSB Phase Noise Floor
VCO Negative Resistance Amplifier
Supply Current (Enabled)
Supply Current (Standby)
Input Frequency Range
Phase Noise at 10kHz Offset
Phase Noise at 100kHz Offset
VCO Output Buffer
Supply Current (Enabled)
Supply Current (Standby)
Frequency Range
IF LO Input
Frequency Range
Level
Division Ratios
Notes Min.
–
1
–
5
90
0.5
2
–
40
-10
95
80
–
94
–
–
1
–
93
40
91
–
91
–
–
1
–
40
92
40
-10
–
Typ.
Max.
Unit
5
1
–
–
–
–
–
-4
–
2.5
-198
2
1
–
-110
-125
4
1
–
–
-5
2 or 4
–
mA
–
µA
30
–
8191
MHz
Vp-p
500
600
–
32767
–
–
kHz
MHz
dBm
mA
dBc/Hz
–
mA
–
µA
400
MHz
–
dBc/Hz
–
dBc/Hz
–
mA
–
µA
600
MHz
600
MHz
0
dBm
–
Notes:
90. Sinewave or clipped sinewave.
91. With external components forming an 180MHz VCO, as shown in Figure 13/Table 11 and
measured after the on-chip divide by 2.
92. Input to VCOP and/or VCON pins, VCO Negative Resistance amplifier disabled, see
section 6.2.1).
93. Operation will depend on the choice and layout of external resonant components. Above
400MHz reliability of operation under all conditions cannot be guaranteed and it is
recommended that an external VCO be used.
94. 1Hz Normalised Phase Noise Floor (PN1Hz) can be used to calculate the phase noise
within the PLL loop bandwidth by: Measured Phase Noise (in 1Hz) = PN1Hz + 20log₁₀(N) +
10log₁₀(f_comparison); f_comparison = f_ref x ( 1 / M ), see also section 5.4.1.
95. When using an external VCO see the note at the end of section 4.5.
 2015 CML Microsystems Plc
54
D/991_992/20