CMX991 Datasheet, PDF (46/56 Pages) CML Microcircuits – Two-mode demodulator

RF Quadrature Transceiver / RF Quadrature Receiver
CMX991/CMX992
0
-5
-10
-15
-20
-25
-30
-35
25
50
75
100
125
150
TxIF MHz
45MHz, IFH='0'
60MHz, IFH='0'
45MHz, IFH='1'
60MHz, IFH='1'
Figure 31 Effect of IFH on 45MHz and 60MHz Transmitter IF Filters
7.13 Variation in I/Q dc Offset with Temperature
7.13.1 Overview
All I/Q RF mixer designs exhibit dc offset generation in receivers and LO leakage resulting from dc offsets
in transmitters. Such dc offsets, if not properly compensated, can reduce the effective dynamic range of a
receiver and degrade modulation accuracy in transmitters. Receiver offsets are caused by a range of
effects including nonlinear mixing of unwanted frequencies leaking into the mixer via the RF input or other
routes (e.g. PCB ground plane, on-chip leakage paths, etc.), LO leakage and transistor matching effects.
Additionally, wider system level issues can be a cause where the presence of unwanted signals can
generate dc offsets as a result of finite second order intermodulation performance of the mixer.
Due to this complexity and the associated costs of a hardware solution to remove dc offsets from an I/Q
mixer design it is usual to apply a dc offset compensation process in host software which allows the radio
system engineer to maximise radio performance. Software is also preferred because dc offset mitigation
strategies are typically optimised for a particular RF system (i.e. dependent on the air-interface
characteristics). In a receiver this process typically involves measuring the dc offset at the baseband I/Q
signal pins and applying a suitable offset compensation during the subsequent signal processing. For
further information see also section 5.2.4.
7.13.2 Variation of Receiver I/Q Offsets
The change in the I/Q dc offset over temperature can be an important parameter for the operation of a
correction scheme. Assuming the absolute offset is normalised at +20°C then the offset variation over the
full operating temperature range (-40°C to +85°C) is typically only a few mV however designers are
recommended to assume a maximum variation of up to ±10mV. The slope of the variation is not
guaranteed as it varies between devices and between I and Q channels on a particular device. The
variation over -10°C to +55°C is typically half the variation over the full temperature range.
 2015 CML Microsystems Plc
46
D/991_992/20