CMX7861 Datasheet, PDF (47/58 Pages) CML Microcircuits – Digital Channel Filters

CMX7861 FirmCODEC^® Programmable Baseband Interface
CMX7861
INPUT 1
(or I for I/Q
based systems),
and INPUT 3
INPUT 2
(or Q for I/Q
based systems)
and INPUT 4
ADC
1
ADC
2
OUTPUT 1 (or I for I/Q
based systems),
OUTPUT 3, OUTPUT 4
OUTPUT 2 (or Q for I/Q
based systems),
OUTPUT 3, OUTPUT 4
DAC
1
DAC
2
Decimate
ADC
Sample
Time
Stamp
ADC/DAC
Sample
Synchroniser/Timer
Filtering
Operations
RSSI
Configuration and
Task Processor
Interpolate
DAC
Sample
Sync
Filtering
Operations
Time Reg
Time Int Reg
FIFO
FIFO
Figure 28 ADC/DAC Sample Timing Synchronisation
The CMX7861 will count at the selected sample rate and output the counter value in the Sample Time -
$7D read. When in receive each input sample will be time stamped with the sample time, the time stamp
can be optionally read using the Receive FIFO. Using this mechanism the time of arrival of a received
framesync can be determined.
Using the ‘Tx Time Block’, which is described in section 7.4.12, a transmission can be scheduled to
appear at a specified sample time. As the CMX7861 contains a single counter for input and output
samples the result is a transmission at a precise time delay from the received framesync.
The sample counter will run even when the ADCs or DACs are inactive, allowing low-power operation
without losing time synchronisation. To further save overall system power the counter can be compared
to the Sample Timer Interrupt - $65 write register by the CMX7861 and when the two are equal the
CMX7861 will interrupt the host microcontroller.
7.8 Codec And Modem Mode Descriptions
7.8.1 Codec Mode
Codec mode provides the ability to sample at rates up to 72kHz and provides a signal bandwidth of
30.96kHz with that sample rate. With this bandwidth constraint, the FirmCODEC provides ADCs and
DACs to sample or reproduce any arbitrary waveform, for example, left/right stereo or control signals.
Whilst in Codec mode the CMX7861 provides optional user-programmable filtering on the input signal,
and on the output signal. Filter design is straightforward, requiring an understanding of normal filter design
and interpolation by 2. ADC and DAC roll off can be ignored because compensation is automatic.
Limited filter choices are possible when in codec mode. When in transmit either the codec mode filter or a
user-programmable filter must be selected using Program Register P4.1. When in receive the ADC
Compensation filter must be selected using Program Register P4.1. These constraints limit the value of
Program Register P4.1 to $0102 or $0802. The receive user filter in codec mode is configured using
Program Block 10 – Custom Rx Codec Mode Filter. This filter becomes active by selecting codec mode,
and inactive when selecting modem mode.
 2012 CML Microsystems Plc
Page 47
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