CMX7861 Datasheet, PDF (30/58 Pages) CML Microcircuits – Digital Channel Filters

CMX7861 FirmCODEC^® Programmable Baseband Interface
Basic Receive Operation (the ADCs are operating)
CMX7861
The following is an example of receiving I/Q samples when the device is used in I/Q mode
Note: for this example, an ‘ADC1 sample’ refers to an I sample, and an ‘ADC2’ sample refers to a Q
sample.
C-BUS Operation
Write $8000 to FIFO
Control - $50 write
-
Action
Flush the Rx FIFO
Apply input signal
Write $0403 to Mode
Register- $6B write
Start reception
Poll the Receive FIFO
Level - $4F read
register, wait until there
are at least 4 data bytes
in the Rx FIFO
Read the Rx FIFO Word
– see Receive FIFO
Data/Control - $4C,
$4D, $4E read
Wait until there is one
sample block in the Rx
FIFO
Read start flag, ADC1
upper
Read the Rx FIFO Data
Byte register – see
Receive FIFO
Data/Control - $4C,
$4D, $4E read
Read ADC1 lower
Read the Receive FIFO
Data Byte (see Receive
FIFO Data/Control -
$4C, $4D, $4E read) 2
more times
Poll the Receive FIFO
Level - $4F read
register, wait until there
are at least 4 data bytes
in the Rx FIFO
Read the Receive FIFO
Data Byte (see Receive
FIFO Data/Control -
$4C, $4D, $4E read) 4
more times
-
Retrieve the ADC2
sample: ADC2 upper,
ADC2 lower
Wait until there is a
second sample block in
the Rx FIFO
Retrieve the ADC1 and
ADC2 samples: ADC1
upper, ADC1 lower,
ADC2 upper, ADC2
lower
Repeat as required
-
End of reception
Description
To ensure that no data is remaining from
previous sample reception
The input signal should contain a waveform of
significant amplitude and within the bandwidth of
the CMX7861, given its ADC configuration
Initiates reception of ADC1/ADC2 samples.
These will propagate through the CMX7861 and
become available in the Rx FIFO
A sample block is available, this will be read in
the following steps
Read the Rx FIFO Word register and verify that
the most significant bit is set. This indicates the
start of a sample block. The lower 8 bits of the
value returned are the 8 most significant bits of
the ADC1 sample.
Reading the data byte only is more efficient than
reading the whole Rx FIFO Word. The value
returned is the 8 least significant bits of the
ADC1 sample. This step may be combined with
the one below using streaming C-BUS to
improve efficiency further.
The ADC2 sample is read from the Receive
Data FIFO.
A sample block is available, this will be read in
the next step
Another ADC1/ADC2 sample block is read from
the Rx FIFO. Streaming C-BUS may be used to
reduce transfer overhead.
The last 2 steps may be repeated as many
times as required. It is possible to wait for a
higher Rx FIFO fill level, and to stream many
sample blocks from the CMX7861 at once.
Once enough samples have been received a
mode change (using the Mode Register- $6B
write register) will stop reception.
 2012 CML Microsystems Plc
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