CMX7861 Datasheet, PDF (1/58 Pages) CML Microcircuits – Digital Channel Filters

CML Microcircuits
COMMUNICATION SEMICONDUCTORS
CMX7861
FirmCODEC^®
D/7861_FI-1.x/2 June 2012
DATASHEET
7861FI-1.x Programmable Baseband Interface
Advance Information
Features
 Dual Channel Codecs
o Can operate in modem or codec mode
o Two ADCs 16 bit
o Two DACs 14 bit
o Programmable input and output gain
o Differential/single ended inputs/outputs
 Digital Channel Filters
o Two fully-programmable digital filters
o Filter design and configuration support
 Auxiliary ADCs
o Four 10-bit DACs
o Autonomous RAMDAC sequencer
 Auxiliary ADC
o One 10-bit ADC with four-input MUX
o ADC averaging, trip on high/low ‘watch’ modes
 Auxiliary GPIO
o Four programmable input/outputs
 Auxiliary Synthesised Clock Generators
o Two programmable clock outputs
 C-BUS Host Serial Interface
o SPI-like with register addressing
o Read/write 128-byte FIFOs and data buffers
o Streamline transfers, low host service latency
 Master SSP Interface
o External slave device control
o Serial Flash connection
o Pass-through (Thru-port) mode expands host
C-BUS/SPI capacity
Features Cont.
 Low-power 3.0V to 3.6V operation
 Multiple power-saving options
 Small 64-pin VQFN Package
 Evaluation support
o PE0601-7861 Evaluation kit
o PE0002 Interface card
Applications
 General-purpose DSP analogue/digital
interface
o Sensors
o Control systems
o Telemetry/SCADA/data modems
 High Performance Narrowband Data Radio
o DMR
o APCO P25
o Software Defined Radio (SDR)
o 6.25kHz to 25kHz RF channel spacings
o worldwide compatibility e.g. ETSI, FCC,
ARIB, FCC Part 90 per spectral efficiency
requirements
 High Performance I/Q Radio Interface
o Tx and Rx: ‘direct connect’ to zero IF
transceiver
o Simple external RC filters
o Digital filter configurable for multiple RF
channel spacings (Rx), Default is for DMR
o I/Q trims
Analogue
System/Signals
Dual Channel Codec
Channel 1 ADC
Channel 2 ADC
Channel 3 DAC
Channel 4 DAC
Auxiliary Operations
ADC
DACs
GPIO
Programmable Digital Filter 1
Programmable Digital Filter 2
Sample Buffers
ADC/DAC Sync
Clock Generation
Power Management
‘Smart’
Function
Engine
FIFO
Configuration
C-BUS
Registers
Function Image™
Clocks Synths
Aux SSP
CMX7861 FirmCODEC®
DSP
Microcontroller
This document contains:
Datasheet
User
Manual
 2012 CML Microsystems Plc