FX506 Datasheet, PDF (3/17 Pages) Sanyo Semicon Device – High-Current Switching Applications

Pin Number Function
DIL Quad
FX506P FX506LG
FX506LS
14
Compression Capacitor: External components connected to this pin provide the required
compression time-constant. See Figure 2.
15
Audio Output (Rx): The received audio output from the Post-Process path. This output is data
selected and when powersaved is held at V_BIAS.
16
VCO Ref. Drive (Tx) Output: The output to drive the modulation reference oscillator. This output
is data selected and when powersaved is held at V_BIAS. To prevent any d.c. level at this output
causing incorrect frequency selection it is recommended that a.c. coupling components as shown
in Figure 2 are employed. For modulation down to near d.c., these components should be by-
passed.
17
VCO Drive (Tx) Output: The output to drive the modulation VCO. This output is data selected
and when powersaved is held at V .
BIAS
18
R.S.S.I.: The input to the Squelch Selection circuitry from the radio's Received Signal Strength
Indicator output. A data selected input.
19
Noise Input: The noise level can be applied to this pin. This would be the Noise Output integrated
by external components, as indicated in Figure 2, or an externally produced noise level.
20
Noise Output: The output of the on-chip “squelch noise rectifier.” This output is a half-wave
rectified d.c. level that can be applied to the Noise Input via external integrating components. This
output could also be used by an external signal detector circuit. This output level is at V for no
BIAS
input. See Figures 2, 3 and 4.
21
Squelch Drive: A TTL compatible output. The inputs to the comparator are: the logically selected
threshold level from the Digital-to-Analogue converter and the selected noise input. A logic “0”
signifies that the noise threshold has been exceeded.
22
Serial Clock: The externally produced serial data loading clock input. See Figure 5.
This input has an internal 1MΩ pullup resistor.
23
Serial Data: The controlling, 47-bit serial data input. With Chip Select maintained at a logic “0” the
serial data is entered at this pin, loaded bit 46 first, bit 0 last.
Detailed information on the allocation and function of serial data bits (0 to 46) is given in tabular
form on later pages. Data load timing should be carried out as described in Figure 5. This input
has an internal 1MΩ pullup resistor.
24
Chip Select: The data loading control function. During serial loading this input should be operated
as shown in Figure 5. New data is latched on the rising edge of this waveform.
This input has an internal 1MΩ pullup resistor.
3