FX506 Datasheet, PDF (10/17 Pages) Sanyo Semicon Device – High-Current Switching Applications

Serial Control Bits – Loading and Timing Information
SERIAL CLOCK IN
t _DS
Data Clocked
t _PWH
[1]
[1]
t _PWL
[2]
t _DH
bit 46 - loaded first
SERIAL DATA IN
bit 45
t _CSS
CHIP SELECT
Fig.5 Data Load Timing Diagram
bit 44
bit 0 - loaded last
47-bit Data Word Latched
[3]
t _CSH
Data Loading
Serial Data bits, whose functions are described on the previous pages, are loaded to the FX506 using
the timing format illustrated on this page. All 47 bits must be loaded. Data is loaded bit 46 first, bit 0 last.
Function
Serial Clock
[1]
‘High’ Pulse Width
t
PWH
‘Low’ Pulse Width
t
PWL
Serial Data
[2]
Data Set-Up Time
t_DS
Data Hold Time
t_DH
Chip Select
[3]
Select Set-Up Time
t
CSS
Select Hold Time
t
CSH
Min.
600
600
360
120
600
600
Typ.
–
–
–
–
–
–
Max.
–
–
–
–
–
–
Unit
ns
ns
ns
ns
ns
ns
[1]
The Serial Clock pulses do not have to be symmetrical, as shown above, but pulse lengths must
conform to the “minimum” time specification.
[2]
Individual data bits (logic “1” or “0”) are loaded to the device on the rising edge of the input Serial
Data Clock pulse. The data hold period (t ) is to ensure that the data level is steady when it is
DH
sampled.
[3]
The full 47-bit data word is latched into the device on the rising edge of the Chip Select waveform,
at this time the loaded data is acted upon and the circuit configuration/settings will change.
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