FX829 Datasheet, PDF (21/34 Pages) CML Microcircuits – Baseband Signal Processor

Baseband Signal Processor
FX829
The FX829 should be programmed in the following manner:
1. Perform a General Reset when first applying power to the FX829.
2. Program the FX829 configuration whilst in powersave.
e.g. UK/F, MIC, B/W, 1200/2400, DTMF0-3,
DTMFHI, DTMFLO, TXIDLEM, RXDATAM, TXDATAM,
RX SYNC WORD PRIME, SYNT PRIME, SYNC PRIME,
MOD1, MOD2, RX SYNC WORD and AUDIO ATTENUATOR.
3. Take the appropriate parts of the FX829 out of powersave by enabling:
AMP1, AMP2, MOD1, MOD2, AUDIO and (DTMFEN or FFSKTX or FFSKRX).
4. In DTMF Tx mode, a DTMF tone will be generated for the duration that DTMFEN is set to “1”.
5. In FFSK Rx mode, wait for an interrupt (IRQN = “0”) or poll the STATUS register. Remember
that all status flags are reset after reading the STATUS register.
(a) If RXSYNCWORDF, SYNTF or SYNCF become set to “1”, the corresponding
synchronisation word has been detected. This indicates the start of valid Rx data. The
checksum calculation will be automatically reset. Note that the timing of RXDATAF will be
re-aligned by the generation of a SYNC, SYNT or RX SYNC WORD interrupt.
(b) When RXDATAF subsequently becomes set to “1”, read the Rx data from the RXDATA
register. (Note that RXDATAF will be set every 8 bits regardless of whether valid Rx data is
being received or not. Sync and checksum patterns should be considered for validating the
data).
(c) If RXSUMF becomes set to “1”, then all of the Rx data sent (starting after the
synchronisation word and terminating with a checksum) will have been correctly received.
Note that it is necessary to know in advance what message length is expected, in order to
determine at which point RXSUMF is valid (i.e. after the interrupt for the second checksum
data byte being received has occurred). The RXSUMF bit is invalid at all other times. When
RXSUMF becomes set to “1”, the last two bytes of Rx data received will represent the two-
byte checksum transmitted. The first checksum byte will already have been read from the
RXDATA register, the last byte is available to be read, as the RXDATAF bit will also have
been set to “1”.
6. In FFSK Tx mode, wait for an interrupt (IRQN = “0”) or poll the STATUS register. Remember that
all status flags are reset after reading the STATUS register.
(a) Do not send Tx data until the TXDATAF bit has been set to “1”. When the TXDATAF bit is
next set to “1”, write the first byte of Tx data to the TXDATA register. If the transmit buffer is
empty, this data will be transmitted immediately, causing the TXDATAF bit to be set to “1”
approximately one FFSK bit-period after the TXDATA register has been loaded with data.
(Any TXIDLEF bit set upon entering FFSK Tx mode should be ignored).
(b) The next byte of Tx data should be written to the TXDATA register as soon as the TXDATAF
bit has been set to “1”. Once this has been done, the TXDATAF bit will again be set to “1”
eight FFSK bit-periods after the TXDATA register was loaded with the second byte of data.
© 1997 Consumer Microcircuits Limited
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