FX829 Datasheet, PDF (19/34 Pages) CML Microcircuits – Baseband Signal Processor

Baseband Signal Processor
FX829
Checking
The checksum checker performs two tasks:
It takes the first n-1 bits of a received (n = 8m + 16 bits) message, inverts bit n-1, and divides them
modulo-2, by the generating polynomial:
X¹⁵ + X¹⁴ + X¹³ + X¹¹ + X⁴ + X² + 1
The 15 bits remaining in the polynomial divider are checked for all zero.
Secondly, it generates an EVEN parity bit from the first n-1 bits of a received message and compares
this bit with the received parity bit (bit n). See Figure 6.
If the 15 bits in the polynomial divider are all zero, and the two parity bits are equal, then the RXSUMF
bit (STATUS register bit 6) is set. This is updated and latched every 8 bits, starting at the bit
immediately after the initialisation of the bit counter. This initialisation takes place on detection of
frame synchronisation, i.e. the matching of received data to the SYNC, SYNT or RX SYNC WORD.
Note that the checksum is calculated on the received data before it is double buffered (see Figure 4).
n = the number of bits in the received message
m = the number of bytes of transmitted data, excluding checksum
Figure 6 Checksum Checking
© 1997 Consumer Microcircuits Limited
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