FX829 Datasheet, PDF (11/34 Pages) CML Microcircuits – Baseband Signal Processor

Baseband Signal Processor
FX829
MIC
(Bit 1)
When this bit is "1", the MIC input is enabled and the AMP1 (DEMODIN) input is
disabled.
When this bit is "0", the AMP1 (DEMODIN) input is enabled and the MIC input is
disabled.
B/W
(Bit 0)
When this bit is "1", the bandwidth of the audio path is set wide for 20kHz/25kHz
RF channel spacing.
When this bit is "0", the bandwidth of the audio path is set narrow for 12.5kHz RF
channel spacing.
CONTROL 2 Register (Hex address $11)
This register is used to control the functions of the device as described below:
CHKSUM
(Bit 7)
In the Tx mode, when this bit is "1", the checksum generator is enabled. All
complete bytes that are transmitted after this time are used in the checksum
calculation.
When this bit goes from "1" to "0", the checksum generator will complete its
calculations on the current byte and the result will be sent as the next two bytes of
transmitted data.
In the Rx mode, the "0" to "1" transition of the CHKSUM bit is used at the start of
the next byte received at DEMODIN to manually reset the Rx checksum
calculation, see Figure 4. The calculation can also be reset automatically by a
SYNC, SYNT, or RX SYNC WORD detection - see CONTROL 3 / IRQ ENABLE
Register. In this case, the Rx checksum calculation starts with the first data byte
after the 2-byte sync word has been detected. The CHKSUM bit can be reset to
"0" at any time. The result of the checksum is made available in the STATUS
Register after the reception of every complete byte (See RXSUMF bit of the
STATUS Register).
Note that the device is designed to work with any message length, and as a
consequence it is not aware of the position of the checksum within the incoming
data message. It thus performs a checksum assessment after every received
byte. The controlling software should use its knowledge of the system message
length in order to determine which RXSUMF reading is valid, i.e. after the second
of the two checksum bytes has been received.
The timing of data bytes relative to the checksum bit is shown in Figures 3 and 4.
© 1997 Consumer Microcircuits Limited
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D/829/4