CM6571 Datasheet, PDF (42/63 Pages) C-Media Electronics – USB 2.0 full speed-compliant

CM6571
USB Audio Sound Chip
9.2 Mode state diagram and power management
The following graphs are two Mode Switch State Diagrams and corresponding power level (level 0-4) for Mode_Sel and
I2C interface respectively:
Mode State Diagram Controlled by Two Mode_Sel (1,0) Pins
No
Power
Power and
clock supplied
Initialization
(Boot / Get
parameters/codes
from Baseband)
00
01
10
11
Power
01/10/11 ^Down
00
ENC
On
00
11
10
01
Bypass
11
Suspend
01
10
00
Power Down Mode－
 Digital power level 0:
No power
 Analog power level 0:
Minimum analog power
consumption
ENC On Mode－
Bypass Mode－
Suspend Mode－
 Digital power level 4:  Digital power level 3: ^{ Digital power level 1:}
Normal operation
By-pass DSP core
Digital core only
 Analog power level 4: processing
consume static power
Normal operation
 Analog power level 4: ^{ Analog power level 1:}
Normal operation
Analog keeps digital core
LDO voltage on
Figure 9.1 Mode State Diagram (by Mode_Sel pins)
Revised: Nov. 2012
Page 42 / 63
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