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| CM6571 Datasheet, PDF (35/63 Pages) C-Media Electronics – USB 2.0 full speed-compliant | |||
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CM6571
USB Audio Sound Chip
8.6 I2S control description
8.6.1 I2S format description
8.6.1.1 I2S interface settings
I2S has three clock signals, MCLK, BCLK and LRCK, and one data line DOUT. The I2S clock symbols are as follows:
ï® MCLK = main clock
ï® BCLK = bit clock
ï® LRCK = left and right clock
8.6.1.2 I2S bus basics
Both master and slave modes of I2S are supported. I2S DAC Master mode means BCLK and LRCK are provided as shown
below (left). On the contrary, slave mode means BCLK and LRCK are provided by the I2S codecs as shown below (right).
I2S
Interface
MCLK
BCLK
LRCK
Codec
I2S
Interface
MCLK
BCLK
LRCK
Codec
Master mode
Slave mode
I2S MASTER/SLAVE BLOCK DIAGRAM
Below figure indicates the basic waveform of I2S. Note that BCLK is generated at the positive edges of MCLK with the
ratios 1:4, and LRCK is generated at the negative edges of BCLK with the ratios 1:64. Data lines are transited at the
negative edges of BCLK and are sampled at the positive edges of BCLK by codecs in the case of playback or recording.
LRCK
Left Channel
Right Channel
BCLK
DIN/
DOUT
1234
MSB
n-1 n
1234
LSB
MSB
I2S Timing Diagram
n-1 n
LSB
Revised: Nov. 2012
Page 35 / 63
www.cmedia.com.tw
Copyright© C-Media Electronics Inc.
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