CM6571 Datasheet, PDF (36/63 Pages) C-Media Electronics – USB 2.0 full speed-compliant

CM6571
USB Audio Sound Chip
For the I²S DAC controller, the audio data is transformed from the parallel format to the serial format before
transmission; then the bit data is shifted out one by one with the MSB first via DOUT signal. If the I²S DAC controller is
set to 32 bits, at least 32 BCLKs must exist in both the LRCK left and right channels. In the same manner, the audio data
is transformed from the coming serial format to the parallel format for an I²S ADC controller.
8.6.1.3 left justified mode
In the I²S DAC controller left-justified mode, the MSB data bit is clocked out at the negative edge of BCLK, which is
aligned to the transition of LRCK. The MSB data bit is clocked out by codecs and sampled at the first positive edge of
BCLK which follows a LRCK transition. The LRCK is high during left-channel transmission and low during right-channel
transmission in the left-justified mode.
LRCK
BCLK
DIN/
DOUT
Left Channel
the MSB is sampled here
Right Channel
where the MSB is clocked out
1234
n-1 n
1234
MSB
LSB
MSB
I2S Left-Justified Mode Timing Diagram
n-1 n
LSB
8.6.1.4 I2S mode
Once the I²S DAC controller is in I²S mode, the MSB data bit is clocked out by the CM6571 at the first negative edge of
BCLK which follows a LRCK transition. The MSB data bit is clocked out by codecs and sampled at the second positive
edge of BCLK which follows a LRCK transition. LRCK is low during left-channel transmission and high during
right-channel transmission in this mode.
LRCK
BCLK
1 BCLK
DIN/
DOUT
Left Channel
the MSB is sampled here
Right Channel
where the MSB is clocked out
1 BCLK
123
n-1 n
123
MSB
LSB
MSB
I²S DAC Controller’s I²S Mode Diagram
n-1 n
LSB
Revised: Nov. 2012
Page 36 / 63
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