CMI8787 Datasheet, PDF (13/28 Pages) C-Media Electronics – High Performance PCI Audio Processor

XAC97_BCLK
XAC97_SDI0
XAC97_SDI1/
XADC1_SDIN1
XAC97_SYNC
XAC97_SDO0
XAC97_SDO1
XAC97_RST0
XAC97_RST1
XAC97_MCLK
XSPI_DIN/
XMSDA
XSPI_CLK/
XMSCL
XSPI_DOUT/
XA1
XSPI_CEN0/
XA0
XSPI_CEN 1/
XCID0
XSPI_CEN 2/
XCID1
XSPI_CEN 3/
XCID2
XSPI_CEN 4/
XEESK
XSPI_CEN 5/
XEEDO
XMSDA/
XSPI_DIN
XMSCL/
XSPI_CLK
XA1/
XSPI_DOUT
C-Media High Performance PCI Audi o Processor
Oxygen^TM HD CMI8787 Datasheet v0.5
63
DI, PU AC97 serial clock input8
62
DI, PD AC97 serial data input 0
58
DI, PD AC97 serial data input 1. This pin is shared with XADC1_SDIN1,
and determined by XSPI_DOUT/XA1 input configuration at the
rising edge of XRST.
61
DO AC97 frame synchronization.
64
DO AC97 serial data output 0.
59
DO AC97 serial data output 1.
60
DO AC97 codec reset 0.
57
DO AC97 codec reset 1.
65
DO AC97 master clock 24.5760M for AC97 codec.
Serial Port Interface
73
DIO, PU SPI data input. This pin is shared with 2-wire master serial data.
74
DIO, PU ^{SPI clock output. This pin is shared with 2-wire master serial}
clock.
75
DIO, PU ^{SPI data output. This pin is shared with 2-wire Codec address A1.}
It is also used as XAC97_SDI1 and XADC1_SDIN1
configuration at the rising edge of XRST (input, 1: XAC97_SDI1,
0: XADC1_SDIN1).
77
DIO, PU ^{SPI chip enable, which select the codec #0 to be controlled. It is}
shared with I2C Codec address A0. It is also used as XGPIO3~4
and SSCL/SSDA configuration (input, 1: GPIO3~4, 0:
SSCL/SSDA) at the rising edge of XRST.
78
DIO, PU ^{SPI chip enable, which select the codec #1 to be controlled}
(output). It is shared with codec ID 0 configuration (input) at the
rising edge of XRST.
79
DIO, PU ^{SPI chip enable, which select the codec #2 to be controlled}
(output). It is shared with codec ID 1 configuration (input) at the
rising edge of XRST.
80
DIO, PU ^{SPI chip enable, which select the codec #3 to be controlled}
(output). It is shared with codec ID 2 configuration (input) at the
rising edge of XRST.
68
DO ^{SPI chip enable, which select the codec #4 to be controlled. It is}
shared with EEPROM serial clock.
69
DO ^{SPI chip enable, which select the codec #5 to be controlled. It is}
shared with EEPROM serial data out.
2-Wire Master Serial Bus
73
DIO, PU 2-wire serial bus data. This pin is shared with SPI data input.
74
DIO, PU ^{2-wire serial bus clock. This pin is shared with SPI clock output.}
75
DIO, PU ^{2-wire serial bus codec address A1. This pin is shared with SPI}
data output. It is also used as XAC97_SDI1 and XADC1_SDIN1
configuration at the rising edge of XRST (input, 1: XAC97_SDI1,
12
C-MEDIA CONFIDENTIAL