CPC7582_1 Datasheet, PDF (15/19 Pages) Clare, Inc. – Line Card Access Switch

switch will remain in the on state no matter the logic
input until the next zero crossing. These switching
characteristics will reduce and possibly eliminate
overall system impulse noise normally associated with
ringing switches. See application note AN-144, Impulse
Noise Benefits of Line Card Access Switches. The
attributes of ringing switch SW4 may make it possible
to eliminate the need for a zero-cross switching
scheme. A minimum impedance of 300 Ω in series
with the ringing generator is recommended.
2.6 Power Supplies
Both a +5 V supply and battery voltage are connected
to the CPC7582. CPC7582 switch state control is
powered exclusively by the +5 V supply. As a result,
the CPC7582BC exhibits extremely low power
dissipation during both active and idle states.
The battery voltage is not used for switch control but
rather as a supply for the integrated secondary
protection circuitry. The integrated SCR is designed to
trigger when pin 2 (T_BAT) or pin 15 (R_BAT) drops 2 to
4 V below the voltage on pin 16 (V_BAT). This trigger
prevents a fault induced overvoltage event at the T_BAT
or R_BAT nodes.
2.7 Battery Voltage Monitor
The CPC7582 also uses the V_BAT voltage to monitor
battery voltage. If battery voltage is lost, the CPC7582
immediately enters the all-off state. It remains in this
state until the battery voltage is restored. The device
also enters the all-off state if the system battery
voltage goes more positive than –10 V, and remains in
the all-off state until the battery voltage goes more
negative than –15 V. This battery monitor feature
draws a small current from the battery (less than 1 μA
typical) and will add slightly to the device’s overall
power dissipation.
2.8 Protection
2.8.1 Diode Bridge/SCR
The CPC7582 uses a combination of current limited
break switches, a diode bridge/SCR clamping circuit,
and a thermal shutdown mechanism to protect the
SLIC device or other associated circuitry from damage
during line transient events such as lightning. During a
positive transient condition, the fault current is
conducted through the diode bridge to ground via
F_GND. Voltage is clamped to a diode drop above
ground. During a negative transient of 2 to 4 V more
negative than the voltage at V_BAT, the SCR conducts
CPC7582
and faults are shunted to F_GND via the SCR or the
diode bridge.
In order for the SCR to crowbar or foldback, the on
voltage (see “Protection Circuitry Electrical
Specifications” on page 10) of the SCR must be less
negative than the V_BAT voltage. If the V_BAT voltage is
less negative than the SCR on voltage or if the V_BAT
supply is unable to source the trigger current, the SCR
will not crowbar.
For power induction or power-cross fault conditions,
the positive cycle of the transient is clamped to the
diode drop above ground and the fault current directed
to ground. The negative cycle of the transient will
cause the SCR to conduct when the voltage exceeds
the V_BAT voltage by two to four volts, steering the
current to ground.
2.8.2 Current Limiting function
If a lightning strike transient occurs when the device is
in the talk state, the current is passed along the line to
the integrated protection circuitry and limited by the
dynamic current limit response of the active switches
during the talk state. During the talk state, when a
1000V 10x1000 μs pulse (GR-1089-CORE lightning)
is applied to the line though a properly clamped
external protector, the current seen at pins 2 (T_BAT)
and pin 15 (R_BAT) will be a pulse with a typical
magnitude of 2.5 A and a duration of less than 0.5 μs.
If a power-cross fault occurs with the device in the talk
state, the current is passed though break switches
SW1 and SW2 on to the integrated protection circuit
and is limited by the dynamic DC current limit
response of the two break switches. The DC current
limit, specified over temperature, is between 80 mA
and 425 mA, and the circuitry has a negative
temperature coefficient. As a result, if the device is
subjected to extended heating due to a power cross
fault, the limited current measured at pin 3 (T_LINE) and
pin 14 (R_LINE) will decrease as the device temperature
increases. If the device temperature rises sufficiently,
the temperature shutdown mechanism will activate
and the device will enter the all-off state.
2.9 Temperature Shutdown
The thermal shutdown mechanism will activate when
the device temperature reaches a minimum of 110° C,
placing the device in the all-off state regardless of
logic input. During thermal shutdown mode, pin 7
(T_SD) will read 0 V. Normal output of T_SD is +V_DD.
R05
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