SA306 Datasheet, PDF (9/14 Pages) Cirrus Logic – 3 Phase Switching Amplifier

Product Innovation From
SA306
The block diagram in Figure 5 illustrates the features of the input and output structures of the SA306. For simplicity,
a single phase is shown.
Figure 5. Input and output structures for a single phase
12k
SC
12k
TEMP
SC
Logic
+
Temp
Sense
_
Ref
Current
Sense
Vdd
Ia'
Vth
I_LIM/DIS1
Ia
UVLO
DIS2
12k
At
Ab
SGND
12k
Lim a
Lim b
Lim c
Gate
Control
Vs
OUT A
PGND
TABLE 2. Truth Table
Comments
0 0 X X X High-Z Top and Bottom output FETs for that phase are turned off.
0 1 <V_th 0 0 PGND Bottom output FET for that phase is turned on.
1 0 <V_th 0 0
VS
Top output FET for that phase is turned on.
1 1 X X X High-Z Both output FETs for that phase are turned off.
X X >V_th
1
X
High-Z
Voltage on Ia, Ib, or Ic has exceeded Vth, which causes I_Lim/Dis1 to go high.
This internally disables Top and Bottom output FETs for ALL phases.
X X X X 1 High-Z Dis2 pin pulled high, which disables all outputs.
XX
X
Pulled
High
X
High-Z
Pulling the I_Lim/Dis1 pin high externally acts as a second disable input,
which disables ALL output FETs.
XX
X
Pulled
Low
0
Determined
by PWM
inputs
Pulling the Dis2 pin low externally disables the cycle-by-cycle current limit
function. The state of the outputs is strictly a function of the PWM inputs.
XX X
X X High-Z If V_S is below the UVLO threshold all output FETs will be disabled.
SA306U