SA306 Datasheet, PDF (7/14 Pages) Cirrus Logic – 3 Phase Switching Amplifier

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SA306
also includes a dead-time generator, which inserts dead time in the outputs in the case of simultaneous switching
of the top and bottom input signals.
At, Bt, Ct: These Schmitt triggered logic level inputs are responsible for turning the associated top side, or upper
P-channel FET outputs on and off. Logic high turns the top P-channel FET on, and a logic low turns the top P-chan-
nel FET off.
Ia, Ib, Ic: Current sense pins. The SA306 supplies a positive current to these pins which is proportional to the cur-
rent flowing through the top side P-channel FET for that phase. Commutating currents flowing through the back-
body diode of the P-channel FET or through external Schottky diodes are not registered on the current sense pins.
Nor do currents flowing through the low side N-channel FET, in either direction, register at the current sense pins. A
resistor connected from a current sense pin to SGND creates a voltage signal representation of the phase current
that can be monitored with ADC inputs of a processor or external circuitry.
The current sense pins are also internally compared with the current limit threshold voltage reference, Vth. If the
voltage on any current sense pin exceeds Vth, the cycle by cycle current limit circuit engages. Details of this func-
tionality are described in the applications section of this datasheet.
I_LIM/DIS1: This pin is directly connected to the disable circuitry of the SA306. Pulling this pin to logic high places OUT
A, OUT B, and OUT C in a high impedance state. This pin is also connected internally to the output of the current
limit latch through a 12kΩ resistor and can be monitored to observe the function of the cycle-by-cycle current limit
feature. Pulling this pin to a logic low effectively disables the cycle-by-cycle current limit feature.
SGND: This is the ground return connection for the V_DD logic power supply pin. All internal analog and logic circuitry
is referenced to this pin. PGND is internally connected to GND through a resistance of a few ohms,. However, it is
highly recommended to connect the GND pin to the PGND pins externally as close to the device as possible. Failure
do to this may result in oscillations on the output pins during rising or falling edges.
V_DD: This is the connection for the 5V power supply, and provides power for the logic and analog circuitry in the
SA306. This pin requires decoupling (at least 0.1µF capacitor with good high frequency characteristics is recom-
mended) to the SGND pin.
DIS2: The DIS2 pin is a Schmitt triggered logic level input that places OUT A, OUT B, and OUT C in a high im-
pedance state when pulled high. DIS2 has an internal 12kΩ pull-down resistor and may therefore be left uncon-
nected.
TEMP: This logic level output goes high when the die temperature of the SA306 reaches approximately 135ºC. This
pin WILL NOT automatically disable the device. The TEMP pin includes a 12kΩ series resistor.
HS: These pins are internally connected to the thermal slug on the reverse of the package. They should be con-
nected to GND. Neither the heat slug nor these pins should be used to carry high current.
NC: These “no-connect” pins should be left unconnected.
SA306U