CS61318 Datasheet, PDF (9/28 Pages) Cirrus Logic – E1 LINE INTERFACE UNIT

CS61318
data input is not present. In host mode, the trans-
mitter can be set to high impedance by setting the
TxHIZ bit, CR2.1, to “1.”
When any transmit control bit (TAOS or LLOOP)
is toggled, the transmitter outputs will require ap-
proximately 22 bit periods to stabilize. The trans-
mitter will take longer to stabilize when RLOOP is
selected because the timing circuitry must adjust to
the new frequency.
2.4 Transmit All Ones Select
The transmitter provides for all ones insertion at the
frequency of TCLK. If TCLK is absent, then
MCLK is used (or the quartz crystal generated fre-
quency in the absence of MCLK). Transmit all
ones is selected when TAOS, pin 28, (CR1.7 = 1, in
host mode) goes high, and causes continuous ones
to be transmitted on the line (TTIP and TRING).
When TAOS is active, the TPOS and TNEG
(TDATA) inputs are ignored. If Remote Loopback
is in effect, any TAOS request will be ignored.
2.4.1 Receiver
The receiver extracts data and clock from the input
signal and outputs clock and synchronized data.
The Long Haul receiver can receive signals over
the entire range down to -36dB at E1 rates. The in-
coming pulses are amplified, equalized and filtered
before being fed to the comparator for peak detec-
tion, slicing and data recovery. The clock and data
recovery circuit exceeds the jitter tolerance specifi-
cations of ITU-T G.823 and ETSI CTR12. The
RTIP and RRING inputs are biased to an interme-
diate DC level and treat the input signal differen-
tially.
2.4.2 Clock Recovery
The clock recovery circuit is a third-order phase-
locked loop. The clock and data recovery circuit is
tolerant of long strings of consecutive zeros, and
will successfully receive a 1-in-175, jitter-free in-
put signal.
Data on RPOS and RNEG (RDATA), is stable and
may be latched using the falling edge of recovered
clock, RCLK. In host mode, CLKE, pin 28, deter-
mines the clock polarity for which output data is
stable and valid as shown in Table 1. When CLKE
is high, RPOS and RNEG (RDATA) are valid on
the falling edge of RCLK. When CLKE is low,
RPOS and RNEG are valid on the rising edge of
RCLK.
MODE
(pin 5)
CLKE
(pin 28)
DATA
CLOCK
Clock Edge for
Valid Data
LOW
Don’t RPOS RCLK
Care RNEG
Rising
HIGH
LOW
RPOS
RNEG
SDO
RCLK
RCLK
SCLK
Rising
Rising
Falling
HIGH
HIGH RPOS RCLK
RNEG RCLK
SDO SCLK
Falling
Falling
Rising
Table 1. Data Output/Clock Relationship
2.4.3 Jitter Tolerance
The CS61318 has excellent jitter tolerance, accept-
ing as much as 0.35UI of jitter from 10 kHz to
100 kHz without error.
2.4.4 Receiver Line Attenuation Indica-
tion
The LATN pin, pin 18, outputs a coded signal that
represents the signal level at the input of the receiv-
er. As shown in Figure 7, the LATN output is mea-
sured against RCLK to provide the signal level in
7.5 dB increments. In host mode, the receive input
signal level can be read from the Equalizer Gain
register, address 0x12, to greater resolution, divid-
ing the input range into 20 steps of 2 dB incre-
ments.
2.5 Jitter Attenuator
Jitter attenuation can be implemented in either the
transmit (JASEL is low) or receive (JASEL is high)
DS441PP2
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