CS61318 Datasheet, PDF (23/28 Pages) Cirrus Logic – E1 LINE INTERFACE UNIT

CS61318
RNEG/RPOS - Receive Negative Pulse, Receive Positive Pulse, Pins 6 and 7.
Recovered data output on RPOS and RNEG is stable and valid on the rising edge of RCLK in Hardware
Mode. In Host Mode, CLKE determines the edge of RCLK on which RPOS and RNEG are valid. A
positive pulse on RTIP with respect to RRING generates a logic 1 on RPOS; a positive pulse on RRING
with respect to RTIP generates a logic 1 on RNEG.
RDATA - Received Data, Pin 7.
Unipolar data (single-line NRZ) data is output on RDATA when pin 4, TNEG/UBS, is held high.
BPV - Bipolar Violation, Pin 6.
When pin 4 is held high, received bipolar violations are flagged by BPV (RNEG) going high along with
the offending bit output from RDATA. If the HDB3 encoder/decoder is activated, BPV will not flag bipolar
violations resulting from valid zero substitutions.
RTIP,RRING - Receive Tip; Receive Ring, Pins 19,20.
The HDB3 signal received from the line is input via these pins. A 1:1 transformer and appropriate
matching resistors are required as shown in the applications section. Data and clock recovered from the
signal input on these pins is output via RPOS, RNEG, and RCLK.
TTIP, TRING - Transmit Tip; Transmit Ring, Pins 13,16
These pins are the output of the differential transmit driver. The transformer and matching resistors can
be chosen to give the desired pulse height (see Application Schematics).
DS441PP2
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