CS61318 Datasheet, PDF (1/28 Pages) Cirrus Logic – E1 LINE INTERFACE UNIT

CS61318
E1 Line Interface Unit
Features
Description
s E1 Line Interface Unit
s No Crystal Needed for Jitter Attenuation
s Meets CTR-12/TBR-12 Jitter Tolerance and Attenu-
ation Requirements
s Meets ITU-T G.775 Requirements for LOS and AIS
s Meets the BS6450 Transmitter Short-Circuit
Requirements for E1 Applications
s AWG for User Programmable Pulse Shapes
s Line Quality Monitoring Function
s TX Driver High Impedance / Low Power Control
s AIS and LOS Monitoring
s Generation and Detection of Loop Up / Loop Down
Signaling
s Selectable HDB3 Encoding/Decoding
s Selectable Unipolar or Bipolar I/O
s Compliant with:
— ITU-T Recommendations: G.703, G.732, G.775, I.431
— ETSI ETS 300 011, 300 233, CTR 12, TBR 13
— TR-NET-00499
The CS61318 is an E1 primary rate line interface unit.
This device combines the complete analog transmit and
receive circuitry for a single, full-duplex interface E1
rates. The device provides jitter attenuation compliant to
CTR12/TBR13 without requiring an external crystal. Al-
so, the CS61318 is pin and function compatible with the
Level One LXT318.
In addition to a basic hardware control mode, a host
mode is available that gives the user an enhanced func-
tionality via a serial microprocessor interface. The
extended features include custom pulse shape genera-
tion, AIS and LOS monitoring functions, signal strength
monitoring, and generation and detection of loop up and
loop down codes.
ORDERING INFORMATION
CS61318-IL
CS61318-IP
28-pin PLCC
28-pin PDIP
TCLK
TDATA/TPOS
UBS/TNEG
JASEL
E
2N
3
C
O
4
D
E
R
11
JITTER
ATTEN
REMOTE
LOOPBACK
LOCAL
LOOPBACK
(DIGITAL)
RCLK
RDATA/RPOS
BPV/RNEG
D
8E
C
7O
6
D
E
R
JITTER
ATTEN
TRANSMIT
TIMING &
CONTROL
PULSE
SHAPING
CIRCUITRY
ROM / RAM
LINE DRIVERS
TAOS Enable
SERIAL
PORT
REGISTERS & CONTROL LOGIC
LOS/
NLOOP
Clear
TIMING
& DATA
RECOVERY
LLOOP
Enable
EQUALIZER
CONTROL
SLICERS
& PEAK
DETECT
NOISE &
CROSSTALK
FILTERS
LOCAL
LOOPBACK
(ANALOG)
MAGNITUDE
EQUALIZER
AGC
13
TTIP
16
TRING
28
CLKE/TAOS
26
CS/RLOOP
27
SCLK/LLOOP
24
SDI/LBO1
25
SDO/LBO2
18
LATN
19
RTIP
20
RRING
23
INT/NLOOP
12
LOS
INBAND
NLOOP
& LOS
PROCESSOR
RECEIVE
CLOCK
GENERATOR
9
XTALIN
10
XTALOUT
1
MCLK
5
21
22
14
15
MODE RV+ RGND TGND TV+
Preliminary Product Information
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
P.O. Box 17847, Austin, Texas 78760
[phone] FAX: [phone]
http://www.cirrus.com
Copyright © Cirrus Logic, Inc. 1999
(All Rights Reserved)
DS441PP2
AUG ‘99
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