CS4327 Datasheet, PDF (9/36 Pages) Cirrus Logic – Low Cost, 20-Bit, Stereo, Audio D/A Converter

CS4327
transitions during a single LRCK period. Internal
dividers are then set to generate the proper clocks
for the digital filter, delta-sigma modulator and
switched-capacitor filter. Once the MCLK to
LRCK frequency ratio has been detected, the phase
and frequency relationship between the two clocks
must remain fixed. If during any LRCK this rela-
tionship is changed, the CS4327 will reset. Table 1
illustrates the standard audio sample rates and the
required MCLK frequencies.
Fs
(kHz)
32
44.1
48
256x
8.1920
11.2896
12.2880
MCLK (MHz)
384x
12.2880
16.9344
18.4320
512x
16.3840
22.5792
24.5760
Table 1. Common Clock Frequencies
Serial Data Interface
The serial data interface is accomplished via the se-
rial data input, SDATA, serial data clock, SCLK,
and the left/right clock, LRCK. The CS4327 sup-
ports four serial data formats which are selected via
the digital input format pins DIF0 and DIF1. The
different formats control the relationship of LRCK
to the serial data and the edge of SCLK used to
latch the data into the input buffer. Table 2 lists the
formats, along with the associated figure number.
The serial data is represented in 2’s-complement
format with the MSB-first in all four formats.
DIF1
0
0
1
1
DIF0
0
1
0
1
Format
0
1
2
3
Figure
3
3
4
5
Table 2. Digital Input Formats
Formats 0 and 1 are shown in Figure 3. The audio
data is right-justified, LSB aligned with the trailing
edge of LRCK, and latched into the serial input
data buffer on the rising edge of SCLK. Formats 0
and 1 are 16 and 20-bit versions and differ only in
the number of data bits required.
Format 2 is 20-bit left justified, MSB aligned with
the leading edge of LRCK. Data is latched on the
falling edge of SCLK. The format will support 16
and 18-bit inputs if the data is followed by four or
two zeros to simulate a 20-bit input as shown in
Figure 4. A very small offset will result if the 18 or
16-bit data is followed by static non-zero data.
Format 3 is compatible with the I²S serial data pro-
tocol as shown in Figure 5. Notice that the MSB is
delayed 1 period of SCLK following the leading
edge of LRCK and LRCK is inverted compared to
the previous formats. Data is latched on the rising
edge of SCLK. Format 3 is a 20-bit I²S format. 18-
bit or 16-bit I²S can be implemented if the data is
followed by two or four zeros to simulate a 20-bit
input as shown in Figure 5. A very small offset will
result if the 18 or 16-bit data is followed by static
non-zero data.
Serial Clock
The serial clock controls the shifting of data into
the input data buffers. The CS4327 supports both
external and internal serial clock generation modes.
External Serial Clock
The CS4327 will enter the external serial clock
mode if 15 or more high\low transitions are detect-
ed on the SCLK pin during any phase of the LRCK
period. When this mode is enabled, internal serial
clock mode cannot be accessed without returning
to the power down mode.
Internal Serial Clock
In the Internal Serial Clock Mode, the serial clock
is internally derived and synchronous with MCLK.
The internal SCLK / LRCK ratio is always 64 and
operation in this mode is identical to operation with
an external serial clock synchronized with LRCK.
The SCLK pin must be connected to DGND for
proper operation.
The internal serial clock mode is advantageous in
that there are situations where improper serial
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