CS4327 Datasheet, PDF (17/36 Pages) Cirrus Logic – Low Cost, 20-Bit, Stereo, Audio D/A Converter

CS4327
Digital Inputs
MCLK - Clock Input, PIN 8.
The frequency must be either 256x, 384x or 512x the input sample rate (Fs).
LRCK - Left/Right Clock, PIN 7.
This input determines which channel is currently being input on the Serial Data Input pin,
SDATA. The format of LRCK is controlled by DIF0 and DIF1.
SCLK - Serial Bit Input Clock, PIN 9.
Clocks the individual bits of the serial data in from the SDATA pin. The edge used to latch
SDATA is controlled by DIF0 and DIF1.
SDATA - Serial Data Input, PIN 10.
Two’s complement MSB-first serial data of either 16, 18 or 20 bits is input on this pin. The
data is clocked into the CS4327 via the SCLK clock, and the channel is determined by the
LRCK clock. The format for the previous two clocks is determined by the Digital Input Format
pins, DIF0 and DIF1.
DIF0, DIF1 - Digital Input Format, PINS 15, 11
These two pins select one of four formats for the incoming serial data stream. These pins set
the format of the SCLK and LRCK clocks with respect to SDATA. The formats are listed in
Table 2.
DEM0, DEM1 - De-Emphasis Select, PINS 1, 2.
Controls the activation of the standard 50/15 µs de-emphasis filter for either 32, 44.1 or 48 kHz
sample rates.
AUTO_MUTE - Automatic Mute on Idle Channel Input, PIN 12.
When AUTO_MUTE is low the analog outputs are muted following an idle channel detection.
Idle channel is defined as an input of static 1's or static 0's during 8192 consecutive LRCK
cycles. Mute is canceled with the return of active channel input data.
CMFILT - Common Mode Filter, PIN 16
Used to filter the common mode output voltage with a 1 µF capacitor. This pin is not intended
to supply any current and should not be used for the generation of an external bias voltage.
DS190F1
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