CS4327 Datasheet, PDF (11/36 Pages) Cirrus Logic – Low Cost, 20-Bit, Stereo, Audio D/A Converter

CS4327
clock routing on the printed circuit board can de-
grade system performance. The use of the internal
serial clock mode simplifies the routing of the
printed circuit board by allowing the serial clock
trace to be deleted and avoids possible interference
effects.
Auto Mute
An auto-mute function is useful for applications,
such as compact disk players, where the idle chan-
nel noise must be minimized. The CS4327 will au-
tomatically initiate a mute for an idle channel input,
where idle channel is defined as an input of static
1’s or static 0’s during 8192 consecutive LRCK cy-
cles. The mute will be immediately released when
non-idle channel data is applied to either the Left or
Right channels. This feature is selectable and active
only if the AUTO_MUTE pin is low.
De-Emphasis
Implementation of digital de-emphasis requires re-
configuration of the digital filter to maintain the fil-
ter response shown in Figure 6 at multiple sample
rates. The CS4327 is capable of digital de-empha-
sis for 32, 44.1 or 48 kHz sample rates. Table 3
shows the de-emphasis control inputs for DEM 0
and DEM 1.
Gain
dB
0 dB
T1=50 µs
-10 dB
T2 = 15 µs
DEM1
0
0
1
1
DEM0
0
1
0
1
De-emphasis
32 kHz
44.1 kHz
48 kHz
OFF
Table 3. De-Emphasis Filter Selection
Initialization, Calibration and Power-Down
Upon initial power-up, the DAC enters the power-
down mode. The interpolation filters and delta-sig-
ma modulators are reset, and the internal voltage
reference, one-bit D/A converters and switched-ca-
pacitor low-pass filters are powered down. The de-
vice will remain in the power-down mode until
MCLK and LRCK are presented. Once MCLK and
LRCK are detected, MCLK occurrences are count-
ed over one LRCK period to determine the MCLK
/ LRCK frequency ratio. Power is applied to the in-
ternal voltage reference, the D/A converters,
switched-capacitor filters and the DAC will begin a
common mode bias voltage calibration. This ini-
tialization and calibration sequence requires ap-
proximately 2700 cycles of LRCK. The CS4327
will enter the power-down mode, within 1 period of
LRCK, if either MCLK or LRCK is removed. The
initialization sequence, as described above, occurs
when MCLK and LRCK are restored.
An offset calibration can be invoked by changing
the state of Digital Input Format pins, DIF0 and/or
DIF1, for at least 3 LRCK cycle. During calibra-
tion, a common-mode voltage of approximately
1.8 V appears at the outputs, with approximately a
16 kohm output impedance. Following calibration,
the analog output impedance becomes less than
10 ohms and the common mode voltage will move
to approximately 2.3 V.
F1
3.183 kHz
F2 Frequency
10.61 kHz
Figure 6. De-emphasis Filter Response
DS190F1
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