CS4382 Datasheet, PDF (8/42 Pages) Cirrus Logic – 114 dB, 192 kHz 8-Channel D/A Converter

CS4382
SWITCHING CHARACTERISTICS (For KQZ T_A = -10 to +70 °C; VLS = 1.8 V to 5.5 V; Inputs: Logic
0 = GND, Logic 1 = VLS, C_L = 30 pF)
Parameters
MCLK Frequency
Symbol
Min
Typ
Max
Units
(Note 15)
Single Speed Mode
Double Speed Mode
1.024
-
6.400
-
51.2
MHz
51.2
MHz
Quad Speed Mode
6.400
-
51.2
MHz
MCLK Duty Cycle
Input Sample Rate
40
50
60
%
Single Speed Mode Fs
4
-
50
kHz
Double Speed Mode Fs
50
-
100
kHz
Quad Speed Mode Fs
100
-
200
kHz
LRCK Duty Cycle
45
50
55
%
SCLK Pulse Width Low
SCLK Pulse Width High
SCLK Period
t_sclkl
20
-
t_sclkh
20
-
t_sclkw
--------²---------
-
MCLK
-
ns
-
ns
-
ns
(Note 16) t_sclkw
--------⁴---------
-
MCLK
-
ns
SCLK rising to LRCK edge delay
t_slrd
20
-
-
ns
SCLK rising to LRCK edge setup time
t_slrs
20
-
-
ns
SDATA valid to SCLK rising setup time
t_sdlrs
20
-
-
ns
SCLK rising to SDATA hold time
t_sdh
20
-
-
ns
LRCK1 to LRCK2 frequency ratio
(Note 17)
0.25
1.00
4.00
Notes: 15. See Table 5 on page 26 for suggested MCLK frequencies
16. This serial clock is available only in Control Port Mode when the MCLK Divide bit is enabled.
17. The higher frequency LRCK must be an exact integer multiple (1, 2, or 4) of the lower frequency LRCK
.
LRCK
t _slrd
t _slrs
t _sclkh
t _sclkl
SCLK
t _sdlrs
t _sdh
SDATA
Figure 1. Serial Mode Input Timing
8
DS514F1