CS4382 Datasheet, PDF (10/42 Pages) Cirrus Logic – 114 dB, 192 kHz 8-Channel D/A Converter

CS4382
SWITCHING CHARACTERISTICS - CONTROL PORT - I²C FORMAT
(For KQZ T_A = -10 to +70 °C; VLC = 1.8 V to 5.5 V; Inputs: Logic 0 = GND, Logic 1 = VLC, C_L = 30 pF)
Parameter
Symbol
Min
SCL Clock Frequency
f_scl
-
RST Rising Edge to Start
t_irs
500
Bus Free Time Between Transmissions
t_buf
4.7
Start Condition Hold Time (prior to first clock pulse)
t_hdst
4.0
Clock Low time
t_low
4.7
Clock High Time
t_high
4.0
Setup Time for Repeated Start Condition
t_sust
4.7
SDA Hold Time from SCL Falling
(Note 19) t_hdd
0
SDA Setup time to SCL Rising
t_sud
250
Rise Time of SCL and SDA
t_rc, t_rc
-
Fall Time SCL and SDA
t_fc, t_fc
-
Setup Time for Stop Condition
t_susp
4.7
Acknowledge Delay from SCL Falling
(Note 20)
t_ack
-
Max
Unit
100
kHz
-
ns
-
µs
-
µs
-
µs
-
µs
-
µs
-
µs
-
ns
1
µs
300
ns
-
µs
(Note 21)
ns
Notes: 19.
20.
21.
Data must be held for sufficient time to bridge the transition time, t_fc, of SCL.
The acknowledge delay is based on MCLK and can limit the maximum transaction speed.
--------1---5---------
256 × Fs
for Single-Speed Mode,
--------1---5---------
128 × Fs
for Double-Speed Mode,
-------1---5-------
64 × Fs
for Quad-Speed Mode.
SDA
001100 ^ADDR
AD0
R/W ACK
Note 1
DATA
1-8
ACK ^DATA
1-8
ACK
SCL
Start
Stop
Note: If operation is a write, this byte contains the Memory Address Pointer, MAP.
Figure 3. Control Port Timing - I²C Format
10
DS514F1