CS42526 Datasheet, PDF (78/90 Pages) Cirrus Logic – 114 dB, 192 kHz 6-Ch Codec with S/PDIF Receiver

CS42526
11.2.2 Serial Copy Management System (SCMS)
The CS42526 allows read access to all the channel status bits. For consumer mode SCMS compliance,
the host microcontroller needs to read and interpret the Category Code, Copy bit and L bit appropriately.
11.3 User (U) Data E Buffer Access
Entire blocks of U data are buffered using a cascade of 2 block-sized RAMs to perform the buffering as
described in the Channel Status section. The user has access to the E buffer through the control port Data
Buffer which is mapped into the register space of the CS42526. The Data Buffer must first be configured
to point to the address space of the U data. This is accomplished by setting the BSEL bit to ‘1’ in the reg-
ister “Channel Status Data Buffer Control (address 24h)” on page 65.
The user can configure the Interrupt Mask Register to cause an interrupt whenever any data bit changes
are detected when D to E Channel Status buffer transfers occur. If no data bits have changed within the
current transfer of data from D to E, then no interrupt will be generated. This allows determination of the
acceptable time periods to interact with the E buffer. See “Interrupt Mask (address 21h)” on page 64 for
more details.
The U buffer access only operates in two byte mode, since there is no concept of A and B blocks for user
data. The arrangement of the data is as follows: Bit15[A7]Bit14[B7]Bit13[A6]Bit12[B6]...Bit1[A0]Bit0[B0].
The arrangement of the data in each byte is as follows: MSB is the first received bit and is the first trans-
mitted bit. The first byte read is the first byte received, and the first byte sent is the first byte transmitted.
When two bytes are read from the E buffer, the bits are presented in the following arrangement:
A[7]B[7]A[6]B[6]....A[0]B[0].
11.3.1 Non-Audio Auto-Detection
The CS42526 S/PDIF receiver can detect non-audio data originating from AC-3^® or MPEG encoders.
This is accomplished by looking for a 96-bit sync code, consisting of 0x0000, 0x0000, 0x0000, 0x0000,
0xF872, and 0x4E1F. When the sync code is detected, an internal AUTODETECT signal will be asserted.
If no additional sync codes are detected within the next 4096 frames, AUTODETECT will be de-asserted
until another sync code is detected. The AUDIO bit in the Receiver Channel Status register is the logical
OR of AUTODETECT and the received channel status bit 1. If non-audio data is detected, the data will be
processed exactly as if it were normal audio. It is up to the user to mute the outputs as required.
11.3.1a Format Detection
The CS42526 can automatically detect various serial audio input formats. The Receiver Status register
(08h) is used to indicate a detected format. The register will indicate if uncompressed PCM data,
IEC61937 data, DTS-LD data, DTS-CD data, or digital silence was detected. Additionally, the IEC61937
Pc/Pd burst preambles are available in registers 09h-0Ch. See the register descriptions for more informa-
tion.
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DS585PP5