CS42526 Datasheet, PDF (12/90 Pages) Cirrus Logic – 114 dB, 192 kHz 6-Ch Codec with S/PDIF Receiver

CS42526
SWITCHING CHARACTERISTICS (For CQZ, T_A = -10 to +70° C; For DQZ, T_A = -40 to +85° C;
VA=VARX = 5 V, VD =VLC= 3.3 V, VLS = 1.8 V to 5.25 V; Inputs: Logic 0 = DGND, Logic 1 = VLS, C_L = 30 pF)
Parameters
Symbol
Min
Typ
Max
Units
RST pin Low Pulse Width
(Note 12)
PLL Clock Recovery Sample Rate Range
1
-
-
ms
30
-
200
kHz
RMCK output jitter
(Note 14)
-
200
-
ps RMS
RMCK output duty cycle
OMCK Frequency
(Note 15)
(Note 13)
45
1.024
50
55
%
-
25.600 MHz
OMCK Duty Cycle
CX_SCLK, SAI_SCLK Duty Cycle
(Note 13)
40
50
60
%
45
50
55
%
CX_LRCK, SAI_LRCK Duty Cycle
45
50
55
%
Master Mode
RMCK to CX_SCLK, SAI_SCLK active edge delay
t_smd
0
RMCK to CX_LRCK, SAI_LRCK delay
t_lmd
0
Slave Mode
-
15
ns
-
15
ns
CX_SCLK, SAI_SCLK Falling Edge to CX_SDOUT,
t_dpd
SAI_SDOUT Output Valid
-
50
ns
CX_LRCK, SAI_LRCK Edge to MSB Valid
t_lrpd
-
20
ns
CX_SDIN Setup Time Before CX_SCLK Rising Edge t_ds
10
-
-
ns
CX_SDIN Hold Time After CX_SCLK Rising Edge
t_dh
30
-
-
ns
CX_SCLK, SAI_SCLK High Time
t_sckh
20
-
-
ns
CX_SCLK, SAI_SCLK Low Time
t_sckl
20
-
-
ns
CX_SCLK, SAI_SCLK falling to CX_LRCK,
SAI_LRCK Edge
t_lrck
-25
-
+25
ns
Notes: 12. After powering up the CS42526, RST should be held low after the power supplies and clocks are settled.
13. See Table 1 on page 26 for suggested OMCK frequencies
14. Limit the loading on RMCK to 1 CMOS load if operating above 24.576 MHz.
15. Not valid when RMCK_DIV in “Clock Control (address 06h)” on page 52 is set to Multiply by 2.
CX_SCLK
SAI_SCLK
(output)
CX_LRCK
SAI_LRCK
(output)
RMCK
t _smd
t _lmd
Figure 1. Serial Audio Port Master Mode Timing
CX_LRCK
SAI_LRCK
(input)
CX_SCLK
SAI_SCLK
(input)
t _lrck
t _sckh
tsckl
CX_SDINx
CX_SDOUT
SAI_SDOUT
t_{lrpd tds}
tdh
MSB
tdpd
MSB-1
Figure 2. Serial Audio Port Slave Mode Timing
12
DS585PP5