CS42526 Datasheet, PDF (13/90 Pages) Cirrus Logic – 114 dB, 192 kHz 6-Ch Codec with S/PDIF Receiver

CS42526
SWITCHING CHARACTERISTICS - CONTROL PORT - I²C FORMAT (For CQZ, T_A
= -10 to +70° C; For DQZ, T_A = -40 to +85° C; VA=VARX = 5 V, VD =VLS= 3.3 V; VLC = 1.8 V to 5.25 V; Inputs:
Logic 0 = DGND, Logic 1 = VLC, C_L = 30 pF)
Parameter
Symbol
Min
Max
Unit
SCL Clock Frequency
RST Rising Edge to Start
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
Clock Low time
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling
(Note 16)
SDA Setup time to SCL Rising
Rise Time of SCL and SDA
Fall Time SCL and SDA
Setup Time for Stop Condition
Acknowledge Delay from SCL Falling
(Note 17)
f_scl
t_irs
t_buf
t_hdst
t_low
t_high
t_sust
t_hdd
t_sud
t_rc
t_fc
t_susp
t_ack
-
100
kHz
500
-
ns
4.7
-
µs
4.0
-
µs
4.7
-
µs
4.0
-
µs
4.7
-
µs
0
-
µs
250
-
ns
-
1
µs
-
300
ns
4.7
-
µs
-
(Note 18)
ns
Notes: 16.
17.
18.
Data must be held for sufficient time to bridge the transition time, t_fc, of SCL.
The acknowledge delay is based on MCLK and can limit the maximum transaction speed.
2----5--6--1---×^{5-----F---s- for Single-Speed Mode,} 1---2---8--1---×^{5-----F---s- for Double-Speed Mode,} 6---4----1-×^{--5---F---s- for Quad-Speed Mode}
RST
t _irs
S to p
S tart
SDA
SCL
t _buf
t _hdst
t _high
t
lo w
t
hdd
t _sud
t _ack
R e pe ate d
S ta rt _{t rd}
t _hdst
S to p
t _fd
t _fc
t _susp
t _sust
t _rc
Figure 3. Control Port Timing - I²C Format
DS585PP5
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