CS42528_05 Datasheet, PDF (64/91 Pages) Cirrus Logic – 114 dB, 192 kHz 8-Ch Codec with S/PDIF Receiver

6.20.1 PLL UNLOCK (UNLOCK)
Default = 0
Function:
PLL unlock status bit. This bit will go high if the PLL becomes unlocked.
CS42528
6.20.2 NEW Q-SUBCODE BLOCK (QCH)
Default = 0
Function:
Indicates when the Q-Subcode block has changed.
6.20.3 D TO E C-BUFFER TRANSFER (DETC)
Default = 0
Function:
Indicates when the channel status buffer has changed.
6.20.4 D TO E U-BUFFER TRANSFER (DETU)
Default = 0
Function:
Indicates when the user status buffer has changed.
6.20.5 ADC OVERFLOW (OVERFLOW)
Default = 0
Function:
Indicates that there is an over-range condition anywhere in the CS42528 ADC signal path.
6.20.6 RECEIVER ERROR (RERR)
Default = 0
Function:
Indicates that a receiver error has occurred. The register “Receiver Errors (address 26h) (Read Only)”
on page 67 may be read to determine the nature of the error which caused the interrupt.
6.21 Interrupt Mask (address 21h)
7
UNLOCKM
6
Reserved
5
QCHM
4
DETCM
3
DETUM
2
Reserved
1
OverFlowM
0
RERRM
Default = 00000000
Function:
The bits of this register serve as a mask for the interrupt sources found in the register “Interrupt Status
(address 20h) (Read Only)” on page 63. If a mask bit is set to 1, the error is unmasked, meaning that
its occurrence will affect the INT pin and the status register. If a mask bit is set to 0, the error is
masked, meaning that its occurrence will not affect the INT pin or the status register. The bit positions
align with the corresponding bits in the Interrupt Status register.
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