CS42528_05 Datasheet, PDF (53/91 Pages) Cirrus Logic – 114 dB, 192 kHz 8-Ch Codec with S/PDIF Receiver

CS42528
6.7 Clock Control (address 06h)
7
6
5
4
3
2
1
0
RMCK_DIV1 RMCK_DIV0 OMCK Freq1 OMCK Freq0 PLL_LRCK SW_CTRL1 SW_CTRL0 FRC_PLL_LK
6.7.1 RMCK DIVIDE (RMCK_DIVX)
Default = 00
Function:
Divides/multiplies the internal MCLK, either from the PLL or OMCK, by the selected factor.
RMCK_DIV1 RMCK_DIV0 Description
0
0
Divide by 1
0
1
Divide by 2
1
0
Divide by 4
1
1
Multiply by 2
Table 10. RMCK Divider Settings
6.7.2 OMCK FREQUENCY (OMCK FREQX)
Default = 00
Function:
Sets the appropriate frequency for the supplied OMCK.
OMCK Freq1 OMCK Freq0
Description
0
0
11.2896 MHz or 12.2880 MHz
0
1
16.9344 MHz or 18.4320 MHz
1
0
22.5792 MHz or 24.5760 MHz
1
1
Reserved
Table 11. OMCK Frequency Settings
6.7.3 PLL LOCK TO LRCK (PLL_LRCK)
Default = 0
0 - Disabled
1 - Enabled
Function:
When enabled, the internal PLL of the CS42528 will lock to the SAI_LRCK of the SAI serial port.
6.7.4 MASTER CLOCK SOURCE SELECT (SW_CTRLX)
Default = 00
Function:
These two bits, along with the UNLOCK bit in register “Interrupt Status (address 20h) (Read Only)”
on page 63, determine the master clock source for the CS42528. When SW_CTRL1 and SW_CTRL0
are set to '00'b, selecting the output of the PLL as the internal clock source, and the PLL becomes
unlocked, RMCK will equal OMCK, but all internal and serial port timings are not valid.
When the FRC_PLL_LK bit is set to ‘1’b, the SW_CTRLX bits must be set to ‘00’b. If the PLL becomes
DS586F1
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