CS42528_05 Datasheet, PDF (56/91 Pages) Cirrus Logic – 114 dB, 192 kHz 8-Ch Codec with S/PDIF Receiver

CS42528
RCVR_CLK2 RCVR_CLK1 RCVR_CLK0
Description
0
0
0
8.1920 MHz
0
0
1
11.2896 MHz
0
1
0
12.288 MHz
0
1
1
16.3840 MHz
1
0
0
22.5792 MHz
1
0
1
24.5760 MHz
1
1
0
45.1584 MHz
1
1
1
49.1520 MHz
Table 14. Receiver Clock Frequency Detection
6.10 Burst Preamble PC and PD Bytes (addresses 09h - 0Ch)(Read Only)
7
PCx-7
PDx-7
6
PCx-6
PDx-6
5
PCx-5
PDx-5
4
PCx-4
PDx-4
3
PCx-3
PDx-3
2
PCx-2
PDx-2
1
PCx-1
PDx-1
6.10.1 BURST PREAMBLE BITS (PCX & PDX)
Default = xxh
Function:
The PC and PD burst preamble bytes are loaded into these four registers.
0
PCx-0
PDx-0
6.11 Volume Transition Control (address 0Dh)
7
Reserved
6
SNGVOL
5
SZC1
4
SZC0
3
AMUTE
2
1
MUTE SAI_SP RAMP_UP
0
RAMP_DN
6.11.1 SINGLE VOLUME CONTROL (SNGVOL)
Default = 0
Function:
The individual channel volume levels are independently controlled by their respective Volume Control
registers when this function is disabled. When enabled, the volume on all channels is determined by
the A1 Channel Volume Control register and the other Volume Control registers are ignored.
6.11.2 SOFT RAMP AND ZERO CROSS CONTROL (SZCX)
Default = 00
00 - Immediate Change
01 - Zero Cross
10 - Soft Ramp
11 - Soft Ramp on Zero Crossings
Function:
Immediate Change
When Immediate Change is selected, all level changes will take effect immediately in one step.
Zero Cross
Zero Cross Enable dictates that signal-level changes, either by attenuation changes or muting, will
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