English
Language : 

CS42426 Datasheet, PDF (64/67 Pages) Cirrus Logic – 114 dB, 192kHz 6-Ch CODEC WITH PLL
◁
CS42426
DC ELECTRICAL CHARACTERISTICS (TA = 25° C; AGND=DGND=0, all voltages with respect
to ground; OMCK=12.288 MHz; Master Mode)
Parameter
Symbol Min Typ Max Units
Power Supply Current
normal operation, VA=5 V
IA
(Note 22)
VD=5 V
ID
VD=3.3 V
ID
Interface current, VLC=5V (Note 23) ILC
VLS=5 V
ILS
power-down state (all supplies) (Note 24) Ipd
Power Consumption
(Note 22)
VA=5 V, VD=VLS=VLC=3.3 V
normal operation
power-down (Note 24)
VA=5 V, VD=VLS=VLC=5 V
normal operation
power-down (Note 24)
-
90
-
mA
-
150
-
mA
-
100
-
mA
-
250
-
µA
-
250
-
µA
-
250
-
µA
-
780 850
mW
-
1.25
-
mW
-
950 1050 mW
-
1.25
-
mW
Power Supply Rejection Ratio (Note 25)
(1 kHz) PSRR
-
60
-
dB
(60 Hz)
-
40
-
dB
Notes: 22. Current consumption increases with increasing FS and increasing OMCK. Max values are based on
highest FS and highest OMCK. Variance between speed modes is negligible.
23. ILC measured with no external loading on the SDA pin.
24. Power down mode is defined as RST pin = Low with all clock and data lines held static.
25. Valid with the recommended capacitor values on FILT+ and VQ as shown in Figure .
DIGITAL INTERFACE CHARACTERISTICS (For CQ, TA = +25° C; For DQ, TA = -40 to +85° C)
Parameters (Note 26)
Symbol Min
Typ
Max Units
High-Level Input Voltage
Serial Port
0.7xVLS
-
-
V
Control Port VIH 0.7xVLC
-
-
V
Low-Level Input Voltage
Serial Port
-
-
0.2xVLS V
Control Port VIL
-
-
0.2xVLC V
High-Level Output Voltage at Io=2 mA (Note 27)Serial Port
VLS-1.0
-
Control Port VOH VLC-1.0
-
MUTEC, GPOx
VA-1.0
-
-
V
-
V
-
V
Low-Level Output Voltage at Io=2 mA
Serial Port, Control Port, MUTEC, GPOx
Input Leakage Current
Input Capacitance
(Note 27)
VOL
-
Iin
-
-
-
0.4
V
-
±10
µA
8
-
pF
MUTEC Drive Current
-
3
-
mA
Notes: 26. Serial Port signals include: RMCK, OMCK, ADC_SCLK, ADC_LRCK, DAC_SCLK, DAC_LRCK,
ADC_SDOUT, DAC_SDIN1-3 ADCIN1/2
Control Port signals include: SCL/CCLK, SDA/CDOUT, AD0/CS, AD1/CDIN, INT, RST
27. When operating RMCK above 24.576 MHz, limit the loading on the signal to 1 CMOS load.
64
 ▷