CS42426 Datasheet, PDF (62/67 Pages) Cirrus Logic – 114 dB, 192kHz 6-Ch CODEC WITH PLL

CS42426
SWITCHING CHARACTERISTICS - CONTROL PORT - I²C FORMAT (For CQ, T_A
= -10 to +70° C; For DQ, T_A = -40 to +85° C; VA = 5 V, VD =VLS= 3.3 V; VLC = 1.8 V to 5.25 V; Inputs: Logic
0 = DGND, Logic 1 = VLC, C_L = 30 pF)
Parameter
Symbol
Min
SCL Clock Frequency
f_scl
-
RST Rising Edge to Start
t_irs
500
Bus Free Time Between Transmissions
t_buf
4.7
Start Condition Hold Time (prior to first clock pulse)
t_hdst
4.0
Clock Low time
t_low
4.7
Clock High Time
t_high
4.0
Setup Time for Repeated Start Condition
t_sust
4.7
SDA Hold Time from SCL Falling
(Note 16) t_hdd
0
SDA Setup time to SCL Rising
t_sud
250
Rise Time of SCL and SDA
t_rc
-
Fall Time SCL and SDA
t_fc
-
Setup Time for Stop Condition
t_susp
4.7
Acknowledge Delay from SCL Falling
(Note 17)
t_ack
-
Max
Unit
100
kHz
-
ns
-
µs
-
µs
-
µs
-
µs
-
µs
-
µs
-
ns
1
µs
300
ns
-
µs
(Note 18)
ns
Notes: 16.
17.
18.
Data must be held for sufficient time to bridge the transition time, t_fc, of SCL.
The acknowledge delay is based on MCLK and can limit the maximum transaction speed.
2---5---6--1---×^{5-----F---s- for Single-Speed Mode,} 1---2---8--1---×^{5-----F---s- for Double-Speed Mode,} 6---4----1-×^{--5---F---s- for Quad-Speed Mode}
RST
t _irs
Stop
S t a rt
SDA
SCL
t _buf
t _hdst
t _high
t
low
t
hdd
t _sud t _ack
R epe ate d
Start _{t rd}
t _hdst
Stop
t _fd
t _fc
t _susp
t _sust
t _rc
Figure 58. Control Port Timing - I²C Format
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