CS42426 Datasheet, PDF (14/67 Pages) Cirrus Logic – 114 dB, 192kHz 6-Ch CODEC WITH PLL

CS42426
3.4 Clock Generation
The clock generation for the CS42426 is shown in the figure below. The internal MCLK is derived from
the output of the PLL or a master clock source attached to OMCK. The mux selection is controlled by the
SW_CTRLx bits and can be configured to manual switch mode only, or automatically switch on loss of
PLL lock to the other source input.
ADC_LRCK
(slave mode)
PLL (256Fs)
8.192 -
49.152 MHz
PLL_LRCK bit
OMCK
Internal
MCLK
RMCK_DIVx bits
00
2 01
4 10
X2 11
single
speed
256
00
Auto Detect
Input Clock
01
1,1.5, 2, 4
SW_CTRLx bits
(manual or auto
s w itch )
double
speed
128
quad
speed
64
single
speed
4
double
speed
2
quad
speed
1
RMCK
00
01
D AC _LRC K
10
DAC _FMx bits
00
DAC_OLx
or ADC_OLx bits
01
10
not OLM
128FS _{OLM #1}
DAC_SCLK
256FS _{OLM #2}
00
01
ADC_LRCK
10
ADC_FMx bits
00
ADC_OLx and
ADC _SP SELx bits
01
10
not OLM
128FS _{OLM #1}
ADC_SCLK
256FS _{OLM #2}
Figure 6. Clock Generation
3.4.1 PLL and Jitter Attenuation
The PLL can be configured to lock onto the incoming ADC_LRCK signal from the ADC Serial Port and
generate the required internal master clock frequency. There are some applications where low jitter in the
recovered clock, presented on the RMCK pin, is important. For this reason, the PLL has been designed to
have good jitter attenuation characteristics. By setting the PLL_LRCK bit to a ‘1’ in the register “Clock
Control (address 06h)” on page 37, the PLL will lock to the incoming ADC_LRCK and generate an output
master clock (RMCK) of 256Fs. Table 3 below shows the output of the PLL with typical input Fs values
for ADC_LRCK.
The PLL behavior is affected by the external filter component values. Figure 1 shows the required config-
uration of the external filter components. The set of component values required for 32 kHz to 192 kHz
14