CS4205_05 Datasheet, PDF (62/81 Pages) Cirrus Logic – CrystalClear® Audio Codec ’97 for Portable Computing

CS4205
11. CLOCKING
The CS4205 may be operated as a primary or sec-
ondary codec. As a primary codec, the system
clock for the AC-link may be generated from an ex-
ternal 24.576 MHz clock source, a 24.576 MHz
crystal, or the internal Phase Locked Loop (PLL).
The PLL allows the CS4205 to accept external
clock frequencies other than 24.576 MHz. As a
secondary codec, the system clock is derived from
BIT_CLK, which is generated by the primary co-
dec. The CS4205 uses the presence or absence of a
valid clock on the XTL_IN pin in conjunction with
the state of the ID[1:0]# pins to determine the
clocking configuration. See Table 27 for all avail-
able CS4205 clocking modes.
11.1 PLL Operation (External Clock)
The PLL mode is activated if a valid clock is
present on XTL_IN before the rising edge of
RESET#. Once PLL mode is entered, the
XTL_OUT pin is redefined as the PLL loop filter,
as shown in Figure 23. The ID[1:0]# inputs deter-
mine the configuration of the internal divider ratios
required to generate the 12.288 MHz BIT_CLK
output; see Table 27 on page 63 for additional de-
tails. In PLL mode, the CS4205 is configured as a
primary codec independent of the state of the
ID[1:0]# pins. If 24.576 MHz is chosen as the ex-
ternal clock input (ID[1:0]# inputs both pulled high
or left floating), the PLL is disabled and the clock
is used directly. The loop filter is not required and
XTL_OUT is left unconnected. For all other clock
input choices, the loop filter is required. The
ID[1:0] bits of the Extended Audio ID Register
(Index 28h) and the Extended Modem ID Register
(Index 3Ch) will always report ‘00’ in PLL mode.
11.2 24.576 MHz Crystal Operation
If a valid clock is not present on XTL_IN during
the rising edge of RESET#, the device disables the
PLL input and latches the state of the ID[1:0]# in-
puts. If the ID[1:0]# inputs are both pulled high or
left floating, the device is configured as a primary
codec. An external 24.576 MHz crystal is used as
the system clock as shown in Figure 24.
11.3 Secondary Codec Operation
If a valid clock is not present on XTL_IN and either
ID[1:0]# input is pulled low during the rising edge
of RESET#, the device is determined to be a sec-
ondary codec. The BIT_CLK pin is configured as
an input and the CS4205 is driven from the
12.288 MHz BIT_CLK of the primary codec. The
ID[1:0] bits of the Extended Audio ID Register
(Index 28h) and the Extended Modem ID Register
(Index 3Ch) will report the state of the ID[1:0]#
inputs.
Clock Source
XTL_IN
XTL_OUT
220 pF
2.2 kΩ
0.022 uF
DGND
Figure 23. PLL External Loop Filter
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