CS4205_05 Datasheet, PDF (46/81 Pages) Cirrus Logic – CrystalClear® Audio Codec ’97 for Portable Computing

CS4205
5.28 Serial Port Control Register (Index 6Ah)
D15 D14 D13 D12 D11 D10 D9 D8
SDEN 0
0
0
0
0
0
0
D7 D6 D5 D4 D3 D2 D1 D0
0 SDI3 SDI2 SDI1 SDO2 SDSC SDF1 SDF0
SDEN
SDI[3:1]
SDO2
SDSC
SDF[1:0]
Default
Serial Data Output Enable. The SDEN bit enables transmission of serial data on the SDOUT
pin. The SDEN bit routes the left and right channel data from the AC ’97 controller, the digital
mixer, or the digital effects engine to the serial data port. The actual data routed to the serial
data port are controlled through the SDOS[1:0]/AMAP/SM[1:0] configuration in the AC Mode
Control Register (Index 5Eh). SDEN also functions as a master control for the serial data input
ports, the second serial data output port and the serial clock. Setting this bit also disables the
GPIO[1:0] pins and clears the GC[1:0] bits in the GPIO Pin Configuration Register (Index
4Ch). Clearing this bit re-enables the GPIO[1:0] pins and sets the GC[1:0] bits.
Serial Data Input Enable. The SDI[3:1] bits individually enable the reception of serial data on
the SDI[3:1] pins. Each of these bits routes the left and right channel data from the corre-
sponding serial data input port to its associated volume control. These bits can only be set if
the SDEN bit is ‘1’ and will be cleared automatically if SDEN returns to ‘0’. If the SDEN bit is
‘0’, SDI[3:1] are read-only bits and always return ‘0’. If allowed, setting one of these bits also
disables the corresponding GPIO pin and clears the associated GC bit for this pin in the GPIO
Pin Configuration Register (Index 4Ch). Clearing one of these bits re-enables the correspond-
ing GPIO pin and sets the associated GC bit.
Serial Data Output 2 Enable. The SDO2 bit enables transmission of serial data on the SP-
DO/SDO2 pin. The SDO2 bit routes the left and right channel data from the AC ’97 controller
to the second serial data port. The actual slots routed to the second serial data port are con-
trolled through the AMAP/SM[1:0] configuration in the AC Mode Control Register (Index 5Eh).
This bit can only be ‘set’ if the SDEN bit is ‘1’ and will be ‘cleared’ automatically if SDEN re-
turns to ‘0’. Furthermore, the SDO2 bit can only be ‘set’ if the SPEN bit in the S/PDIF Control
Register (Index 68h) is ‘0’. If the SDEN bit is ‘0’ or the SPEN bit is ‘1’, SDO2 is a read-only bit
and always returns ‘0’.
Serial Clock Enable. The SDSC bit enables transmission of a serial clock on the EAPD/SCLK
pin. Serial data can be routed to DACs that support internal SCLK mode without transmitting
a serial clock. For DACs that only support external SCLK mode, transmission of a serial clock
is required and this bit must be set to ‘1’. This bit can only be set if the SDEN bit is ‘1’ and will
be cleared automatically if SDEN returns to ‘0’. Furthermore, the SDSC bit can only be ‘set’
if the EAPD bit in the Powerdown Control/Status Register (Index 26h) is ‘0’. If the SDEN bit
is ‘0’ or the EAPD bit is ‘1’, SDSC is a read-only bit and always returns ‘0’.
Serial Data Format. The SDF[1:0] bits control the format of the serial data transmitted on the
two output ports and the three input ports. All ports will use the same format. See Table 16
for available formats.
0000h
SDF1 SDF0
0
0
Serial Data Format
I²S
0
1
Left Justified
1
0 Right Justified, 20-bit data
1
1 Right Justified, 16-bit data
Table 16. Serial Data Format Selection
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DS489PP4