CS4205_05 Datasheet, PDF (42/81 Pages) Cirrus Logic – CrystalClear® Audio Codec ’97 for Portable Computing

CS4205
CAPS[1:0]
L/R Capture Source Select. The CAPS[1:0] bits control the source of data routed to the L/R
ADC slots, see Table 14 for actual slots used. Table 15 lists the available capture options. If
a reserved source is selected, the capture slot data will be fixed to ‘0’.
MICS
Microphone Capture Source Select. The MICS bit selects the source of data routed to the Mic
ADC slot. If this bit is ‘clear’, the Mic capture slot will receive data from the Mic ADC. If this bit
is ‘set’, the Mic capture slot will receive the left channel data from the first serial data input
port.
TMM
True Mono Mode. The TMM bit controls the source of the stereo-to-mono mixer that feeds
into the mono out select mux. If this bit is ‘clear’, the output of the stereo input mixer is sent
to the stereo-to-mono mixer. If this bit is ‘set’, the output of the DAC direct mode mux is sent
to the stereo-to-mono mixer. This allows a true mono mix that includes the PC Beep and
Phone inputs and also works during DAC direct mode.
DDM
DAC Direct Mode. The DDM bit controls the source of the line output drivers. When this bit is
‘clear’, the CS4205 stereo output mixer drives the line output. When this bit is ‘set’, the
CS4205 audio DACs (DAC1 and DAC2) directly drive the line output.
AMAP
Audio Slot Mapping. The AMAP bit controls whether the CS4205 responds to the Codec ID
based slot mapping as outlined in the AC ’97 2.1 Specification. This bit is shadowed in the
Extended Audio ID Register (Index 28h). Refer to Table 14 for the slot mapping configura-
tions.
SM[1:0]
Slot Map. The SM[1:0] bits define the Slot Mapping for the CS4205 when the AMAP bit is
‘cleared’. Refer to Table 14 for the slot mapping configurations.
SDOS[1:0]
Serial Data Output Source Select. The SDOS[1:0] bits control the source of data routed to the
CS4205 first serial data output port. Table 15 on page 43 lists the available source options. If
a reserved source is selected, the serial output data will be fixed to ‘0’.
SPDS[1:0]
S/PDIF Transmitter Source Select. The SPDS[1:0] bits control the source of data routed to
the S/PDIF transmitter. Table 15 on page 43 lists the available source options.
Default
0080h
See Section 3, Digital Signal Paths, for more information on using the bits in this register to create various digital
signal path options.
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