CS42416 Datasheet, PDF (61/67 Pages) Cirrus Logic – 110 dB, 192kHz 6-Ch CODEC WITH PLL

CS42416
SWITCHING CHARACTERISTICS (For CQ, T_A = -10 to +70° C; For DQ, T_A = -40 to +85° C;
VA = 5 V, VD =VLC= 3.3 V, VLS = 1.8 V to 5.25 V; Inputs: Logic 0 = DGND, Logic 1 = VLS, C_L = 30 pF)
Parameters
Symbol
Min
Typ
Max
Units
RST pin Low Pulse Width
(Note 13)
1
-
-
ms
PLL Clock Recovery Sample Rate Range
30
-
200
kHz
RMCK output jitter
(Note 15)
-
200
-
ps RMS
RMCK output duty cycle
45
50
55
%
OMCK Duty Cycle
(Note 14)
40
50
60
%
DAC_SCLK, ADC_SCLK Duty Cycle
45
50
55
%
DAC_LRCK, ADC_LRCK Duty Cycle
45
50
55
%
Master Mode
RMCK to DAC_SCLK, ADC_SCLK active edge delay t_smd
0
RMCK to DAC_LRCK, ADC_LRCK delay
t_lmd
0
Slave Mode
-
10
ns
-
10
ns
DAC_SCLK, ADC_SCLK Falling Edge to
t_dpd
ADC_SDOUT, ADC_SDOUT Output Valid
-
50
ns
DAC_LRCK, ADC_LRCK Edge to MSB Valid
t_lrpd
DAC_SDIN Setup Time Before DAC_SCLK Rising
t_ds
Edge
-
20
ns
-
10
ns
DAC_SDIN Hold Time After DAC_SCLK Rising Edge t_dh
-
30
ns
DAC_SCLK, ADC_SCLK High Time
t_sckh
20
-
-
ns
DAC_SCLK, ADC_SCLK Low Time
t_sckl
20
-
-
ns
DAC_SCLK, ADC_SCLK rising to DAC_LRCK,
t_lrckd
25
-
SAI_LRCK Edge
-
ns
DAC_LRCK, ADC_LRCK Edge to DAC_SCLK,
t_lrcks
25
-
ADC_SCLK Rising
-
ns
Notes: 13. After powering up the CS42416, RST should be held low after the power supplies and clocks are settled.
14. See Table 2 on page 15 for suggested OMCK frequencies
15. Limit the loading on RMCK to 1 CMOS load if operating above 24.576 MHz.
DAC_SCLK
ADC_SCLK
(output)
DAC_LRCK
ADC_LRCK
(output)
RMCK
t _smd
t _lmd
DAC_LRCK
ADC_LRCK
(in p u t)
DAC_SCLK
ADC_SCLK
(in put)
t _lrckd
t _lrcks
t _sckh
tsckl
DAC_SDINx
ADC_SDOUT
tlrpd tds
tdh
MSB
tdpd
MS B-1
Figure 56. Serial Audio Port Master Mode Timing
Figure 57. Serial Audio Port Slave Mode Timing
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