EP9301 Datasheet, PDF (6/41 Pages) Cirrus Logic – Entry-level ARM9 System-on-chip Processor

EP9301
Entry Level ARM9 System-on-Chip Processor
Processor Core - ARM920T
The ARM920T is a Harvard architecture processor with
separate 16-kbyte instruction and data caches with an 8-
word line length but a unified memory. The processor
utilizes a five-stage pipeline consisting of fetch, decode,
execute, memory, and write stages. Key features include:
• ARM (32-bit) and Thumb (16-bit compressed)
instruction sets
• 32-bit Advanced Micro-Controller Bus Architecture
(AMBA)
• 16 kbyte Instruction Cache with lockdown
• 16 kbyte Data Cache (programmable write-through or
write-back) with lockdown
• MMU for Linux^®, Microsoft^® Windows^® CE and other
operating systems
• Translation Look Aside Buffers with 64 Data and 64
Instruction Entries
• Programmable Page Sizes of 1 Mbyte, 64 kbyte,
4 kbyte, and 1 kbyte
• Independent lockdown of TLB Entries
MaverickKey^™ Unique ID
MaverickKey unique hardware programmed IDs are a
solution to the growing concern over secure web content
and commerce. With Internet security playing an
important role in the delivery of digital media such as
books or music, traditional software methods are quickly
becoming unreliable. The MaverickKey unique IDs
provide OEMs with a method of utilizing specific
hardware IDs such as those assigned for SDMI (Secure
Digital Music Initiative) or any other authentication
mechanism.
Both a specific 32-bit ID as well as a 128-bit random ID is
programmed into the EP9301 through the use of laser
probing technology. These IDs can then be used to
match secure copyrighted content with the ID of the
target device the EP9301 is powering, and then deliver
the copyrighted information over a secure connection. In
addition, secure transactions can benefit by also
matching device IDs to server IDs. MaverickKey IDs
provide a level of hardware security required for today’s
Internet appliances.
General Purpose Memory Interface (SDRAM,
SRAM, ROM, FLASH)
The EP9301 features a unified memory address model
where all memory devices are accessed over a common
address/data bus. Memory accesses are performed via
the Processor bus. The SRAM memory controller
supports 8- and 16-bit devices and accommodates an
internal boot ROM concurrently with 16-bit SDRAM
memory.
• 1 to 4 banks of 16-bit, 66 MHz SDRAM
• Address and data bus shared between SDRAM,
SRAM, ROM, and FLASH memory
• NOR FLASH memory supported
Table B. General Purpose Memory Interface Pin Assignments
Pin Mnemonic
Pin Description
SDCLK
SDCLKEN
SDCSn[3:0]
RASn
CASn
SDWEn
CSn[7:6] and CSn[3:0]
AD[25:0]
DA[15:0]
DQMn[1:0]
WRn
RDn
WAITn
SDRAM Clock
SDRAM Clock Enable
SDRAM Chip Selects 3-0
SDRAM RAS
SDRAM CAS
SDRAM Write Enable
Chip Selects 7, 6, 3, 2, 1, 0
Address Bus 25-0
Data Bus 15-0
SDRAM Output Enables / Data Masks
SRAM Write Strobe
SRAM Read / OE Strobe
SRAM Wait Input
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