CS4222 Datasheet, PDF (5/26 Pages) Cirrus Logic – 20-Bit Stereo Audio Codec with Volume Control

SWITCHING CHARACTERISTICS - CONTROL PORT
(TA = 25°C VD, VA = 5V±5%; Inputs: logic 0 = DGND, logic 1 = VD, CL = 30pF)
Parameter
Symbol
Min
SPI Mode (SPI/I²C = 0)
CCLK Clock Frequency
fsck
-
RST rising edge to CS falling
tsrs
500
CCLK edge to CS falling
(Note 9)
tspi
500
CS High Time Between Transmissions
tcsh
1.0
CS Falling to CCLK Edge
t_css
20
CCLK Low Time
tscl
66
CCLK High Time
t_sch
66
CDIN to CCLK Rising Setup Time
tdsu
40
CCLK Rising to DATA Hold Time
(Note 10)
t_dh
15
Rise Time of CCLK and CDIN
(Note 11)
tr2
-
Fall Time of CCLK and CDIN
(Note 11)
t_f2
-
Notes: 9. tspi only needed before first falling edge of CS after RST rising edge.
t_spi = 0 at all other times.
10. Data must be held for sufficient time to bridge the transition time of CCLK.
11. For FSCK < 1 MHz
CS4222
Max Units
6
MHz
-
ns
-
ns
-
µs
-
ns
-
ns
-
ns
-
ns
-
ns
100
ns
100
ns
RST
t _srs
CS
t _spi t _css
t _scl t _sch
t _csh
CCLK
t _r2
t _f2
CDIN
t _{dsu t dh}
DS236PP3
5