CS4222 Datasheet, PDF (14/26 Pages) Cirrus Logic – 20-Bit Stereo Audio Codec with Volume Control

CS4222
Serial Audio Data Interface
Serial Audio Interface Signals
The serial interface clock, SCLK, is used for
transmitting and receiving audio data. The active
edge of SCLK is chosen by setting the DSCK bit
in the DSP Port Mode Byte (#6); the default
upon power-up is that data is valid on the rising
edge for both input and output. SCLK is an in-
put from an external source and at least 20
SCLK’s per half period of LRCK are required
for proper operation.
The Left/Right clock (LRCK) is used to indicate
left and right data and the start of a new sample
period. The frequency of LRCK must be equal
to the system sample rate, Fs.
SDIN is the data input pin which drives a pair of
DACs. SDOUT is the output data pin from the
ADC’s.
Serial Audio Interface Formats
The serial audio port supports 5 input and 2 out-
put formats, shown in Figures 6 and 7. These
formats are chosen through the DSP Port Mode
Byte (#5) with the DDO and DDI2/1/0 bits. The
data output format is 20 bits and may be left jus-
tified or I²S compatible depending on the state
of the DDO bit. The input data format is set
with the DDI bits to be left or right justified or
I²S compatible. In addition, the polarity of the
SCLK edge used to clock in/out data from the
CS
CS4222 may be set via the DSCK bit in the DSP
Port Mode Byte (#5). The default input and out-
put format is I²S compatible.
Control Port Interface
The control port is used to load all the internal
settings. The operation of the control port may
be completely asynchronous with the audio sam-
ple rate. However, to avoid potential interference
problems, the control port pins should remain
static if no operation is required.
The control port has 2 modes: SPI and I²C^®,
with the CS4222 operating as a slave device. If
I²C operation is desired, AD0/CS should be tied
to VD or DGND. If the CS4222 ever detects a
negative transition on AD0/CS after power-up,
SPI mode will be selected.
SPI Mode
In SPI mode, CS is the CS4222 chip select sig-
nal, CCLK is the control port bit clock, CDIN is
the input data line from the microcontroller and
the chip address is 0010000. All signals are in-
puts and data is clocked in on the rising edge of
CCLK.
Figure 8 shows the operation of the control port
in SPI mode. To write to a register, bring CS
low. The first 7 bits on CDIN form the chip ad-
dress, and must be 0010000. The eighth bit is a
read/write indicator (R/W), which must be low
to write. Register reading from the CS4222 is
CCLK
CDIN
CHIP
ADDRESS
MAP
DATA
0010000
R/W
MSB
LSB
byte 1 byte n
MAP = Memory Address Pointer
Figure 8. Control Port Timing, SPI mode
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