CDB61584A Datasheet, PDF (5/12 Pages) Cirrus Logic – Dual Line Interface Unit

CDB61584A
Dual Line Interface Unit
EVALUATION HINTS
1) The orientation of pin 1 for the CS61584A is la-
beled "1" on the left side of the socket U7.
2) A jumper must not be placed on header J10
when using the CDB61584A.
3) Component locations R3-R4, R14-R15, C1,
and C12 must have the correct values installed
according to the application. All the necessary
components are included with the evaluation
board.
4) Closing a DIP switch on SW2, SW3, and SW4
towards the label sets the CS61584A control
pin of the same name to logic 1.
5) When performing a manual loopback of the re-
covered signal to the transmit signal at the BNC
connectors, the recovered data must be valid on
the falling edge of RCLK to properly latch the
data in the transmit direction. To accomplish
this, the SW2 switch position labeled "CLKE"
must be closed (logic 1) during Hardware mode
operation or the CLKE bit in the Control A reg-
ister must be set to a 1 during Host mode oper-
ation.
6) Jumpers can be placed on headers J9 and J12 to
provide a ground reference on TRING for 75Ω
coax E1 applications.
7) Properly terminate TTIP/TRING when evalu-
ating the transmit output pulse shape. For more
information concerning pulse shape evaluation,
refer to the Crystal application note entitled
"Measurement and Evaluation of Pulse Shapes
in T1/E1 Transmission Systems."
DS261DB2
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