CDB61584A Datasheet, PDF (3/12 Pages) Cirrus Logic – Dual Line Interface Unit

CDB61584A
Dual Line Interface Unit
provided when headers J7 and J13 are jumpered in
the "AIS" position. The AIS1 and AIS2 LED indi-
cators illuminate when the line interface receiver
has detected the all-ones receive input signal. Re-
sistors R26 and R27 pull-down the TNEG(1,2) in-
puts when coder mode is disabled but headers J7
and J13 are jumpered in the "AIS" position.
Further details concerning Host mode operation are
described in the "readme.txt" file on the enclosed
disk.
Manual Reset
A momentary contact switch SW1 provides a man-
ual reset by forcing the RESET pin of the
CS61584A to a logic 1. Although the transmit and
receive circuitry are continuously calibrated, the
reset can be used to initialize the control logic and
clear the register set. Both channels are powered up
after exiting reset.
TRANSMIT CIRCUIT
The transmit clock and data signals are supplied on
BNC inputs labeled TCLK(1,2), TPOS(1,2), and
TNEG(1,2). In Hardware and Host mode (with
coder mode disabled), data is supplied on the
TPOS(1,2) and TNEG(1,2) BNC inputs in RZ for-
mat. In Host mode with coder mode enabled, data
is supplied on the TDATA(1,2) BNC input in NRZ
format and the TNEG(1,2) BNC input may be used
to indicate the AIS alarm condition as described in
the Host Mode section.
The transmitter output is transformer coupled to the
line interface through 1:1.15 step-up transformers
T1 and T4. The signal is available at either the
TTIP(1,2) and TRING(1,2) binding posts or the
TX(1,2) bantam jacks.
Capacitors C2 and C11 prevent output stage imbal-
ances from producing a DC current that may satu-
rate the transformer and result in an output level
offset. Capacitors C1 and C12 provide transmitter
return loss and are socketed so the value may be
changed according to the application. A 220 pF ca-
pacitor is required for 100Ω twisted-pair T1 or
120Ω twisted-pair E1 applications. A 470 pF ca-
pacitor is required for 75Ω coax E1 applications.
These capacitors are included with the evaluation
board.
Optional diode locations D6-D9 and D10-D13 and
optional resistor locations R8-R9 and R18-R19
provide test locations to evaluate transmit line in-
terface protection circuitry.
RECEIVE CIRCUIT
The receive signal is input at either the RTIP(1,2)
and RRING(1,2) binding posts or the RX(1,2) ban-
tam jacks. The receive signal is transformer cou-
pled to the CS61584A through 1:1.15 step-down
transformers T2 and T3.
The receive line is terminated by resistors R3-R4
and R14-R15 to provide impedance matching and
receiver return loss. They are socketed so the val-
ues may be changed according to the application.
The evaluation board is supplied from the factory
with 38.3Ω resistors for terminating 100Ω twisted-
pair T1 lines, 45.3Ω resistors for terminating 120Ω
twisted-pair E1 lines, and 28.7Ω resistors for termi-
nating 75Ω coaxial E1 lines. Capacitors C4 and
C10 provide a differential input voltage reference.
Optional resistor locations R1-R2, R12-R13, R16-
R17, and R24-R25 provide test locations to evalu-
ate receive line interface protection circuitry.
The recovered clock and data signals are available
on BNC outputs labeled RCLK(1,2), RPOS(1,2),
and RNEG(1,2). In Hardware and Host mode (with
coder mode disabled), data is available on the
RPOS(1,2) and RNEG(1,2) BNC outputs in RZ
format. In Host mode with coder mode enabled,
data is available on the RDATA(1,2) BNC output
in NRZ format and bipolar violations are reported
on BPV(1,2).
DS261DB2
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