CDB61584A Datasheet, PDF (4/12 Pages) Cirrus Logic – Dual Line Interface Unit

CDB61584A
Dual Line Interface Unit
REFERENCE CLOCK
The CDB61584A requires a T1 or E1 reference
clock for operation. This clock may operate at ei-
ther a 1-X rate (1.544 MHz or 2.048 MHz) or an 8-
X rate (12.352 MHz or 16.384 MHz) and can be
supplied by either a quartz crystal, crystal oscilla-
tor, or external reference. The evaluation board is
supplied from the factory with two crystal oscilla-
tors for T1 and E1 operation.
Quartz Crystal
A quartz crystal may be inserted at socket Y1. Be-
cause the crystal operates at an 8-X rate, the SW2
switch position labeled "1XCLK" must be open to
set the 1XCLK pin of the CS61584A to a logic 0
and enable 8-X clock operation.
Crystal Oscillator
A crystal oscillator may be inserted at socket U4 in
the orientation indicated by the silkscreen. Header
J14 must be jumpered in the "OSC" position to pro-
vide connectivity to the REFCLK pin of the
CS61584A. The SW2 switch position labeled
"1XCLK" must be open (logic 0) for 8-X clock op-
eration or closed (logic 1) for 1-X clock operation.
External Reference
An external reference may be provided at the REF-
CLK BNC input. Header J14 must be jumpered in
the "REFCLK" position to provide connectivity to
the REFCLK pin of the CS61584A. The SW2
switch position labeled "1XCLK" must be open
(logic 0) for 8-X clock operation or closed (logic 1)
for 1-X clock operation.
BUFFERING
Buffers U2, U3, and U6 provide additional drive
capability for the BNC and Host mode connections.
The buffer outputs are filtered with an RC network
to reduce the transients caused by buffer switching.
JTAG ACCESS
The CS61584A implements JTAG boundary scan
to support board-level testing. Interface port J56
provides access to the four JTAG pins on the
CS61584A. The J-TMS pin of the CS61584A is
pulled-down by resistor R28 to disable boundary
scan unless the pin is externally pulled high using
the interface port.
TRANSFORMER SELECTION
The evaluation board is supplied from the factory
with Pulse Engineering PE-65388 transformers in-
stalled at locations T1-T4. They are socketed to
permit the evaluation of other transformers.
LINE PROTECTION EVALUATION
Several optional resistor and diode locations on the
transmit and receive line interface allow for the in-
stallation and evaluation of various types of protec-
tion circuitry. Each location is drilled with 60 mil
vias to permit the installation of sockets. These
sockets can be obtained from McKenzie at (510)
651-2700 by requesting part #PPC-SIP-1X32-
620C and are identical to the socket type installed
at the receive resistor locations on the board. They
allow the line protection circuitry to be easily
changed during testing. Note that the traces form-
ing shorts between the socket locations on the line
interface may need to be cut prior to the installation
of protection circuitry.
PROTOTYPING AREA
Four prototyping areas with power supply and
ground connections are provided on the evaluation
board. These areas can be used to develop and test
a variety of additional circuits such as framer de-
vices, system synchronizer PLLs, or specialized in-
terface logic.
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DS261DB2