CS42448_06 Datasheet, PDF (45/64 Pages) Cirrus Logic – 108 dB, 192 kHz 6-In, 8-Out CODEC

CS42448
DAC_DIF2
0
1
1
1
1
DAC_DIF1
1
0
0
1
1
DAC_DIF0
1
0
1
0
1
Description
Right Justified, 16-bit data
One-Line #1, 20-bit
One-Line #2, 24-bit
TDM Mode, 24-bit (slave only)
Reserved
Table 12. DAC Digital Interface Formats
Format
3
4
5
6
-
Figure
Figure 17
Figure 18
Figure 19
Figure 20
-
6.5.4
ADC Digital Interface Format (ADC_DIF[2:0])
Default = 110
Function:
These bits select the digital interface format used for the ADC serial port. The required relationship between
the Left/Right clock, serial clock and serial data is defined by the Digital Interface Format and the options
are detailed in the section “CODEC Digital Interface Formats” on page 31. Refer to Table 9, “Serial Audio
Interface Channel Allocations,” on page 34.
Note: The ADC does not meet Quad-Speed Mode timing specifications in the TDM interface format.
ADC_DIF2
0
0
0
0
1
1
1
1
ADC_DIF1
0
0
1
1
0
0
1
1
ADC_DIF0
Description
0
Left Justified, up to 24-bit data
1
I²S, up to 24-bit data
0
Right Justified, 24-bit data
1
Right Justified, 16-bit data
0
One-Line #1, 20-bit
1
One-Line #2, 24-bit
0
TDM Mode, 24-bit (slave only)
1
Reserved
Table 13. ADC Digital Interface Formats
Format
0
1
2
3
4
5
6
-
Figure
Figure 16
Figure 15
Figure 17
Figure 17
Figure 18
Figure 19
Figure 20
-
6.6 ADC Control & DAC De-Emphasis (Address 05h)
7
ADC1-2_HPF
FREEZE
6
ADC3_HPF
FREEZE
5
DAC_DEM
4
ADC1
SINGLE
3
ADC2
SINGLE
2
ADC3
SINGLE
1
0
AIN5_MUX AIN6_MUX
6.6.1
ADC1-2 High-Pass Filter Freeze (ADC1-2_HPF FREEZE)
Default = 0
Function:
When this bit is set, the internal high-pass filter will be disabled for ADC1 and ADC2.The current DC offset
value will be frozen and continue to be subtracted from the conversion result. See “ADC Digital Filter
Characteristics” on page 13.
DS648F2
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