CS42448_06 Datasheet, PDF (19/64 Pages) Cirrus Logic – 108 dB, 192 kHz 6-In, 8-Out CODEC

CS42448
Notes:
16. After powering up the CS42448, RST should be held low after the power supplies and clocks are settled.
17. See Table 10 on page 43 and Table 11 on page 44 for suggested MCLK frequencies.
18. When operating in TDM interface format, VLS is limited to nominal 2.5 V to 5.0 V operation only.
19. ADC - I²S, Left-Justified, Right-Justified interface formats only. DAC - I²S, Left-Justified, Right-Justified
and Time Division Multiplexed interface formats only.
20. “LRCK” and “SCLK” shall refer to the ADC and DAC left/right clock and serial clock, respectively.
LRCK
t_lcks
SCLK
DAC_SDINx
ADC_SDOUTx
t_ds
t_dh
MSB
t_dpd
MSB
MSB-1
MSB-1
Figure 6. Serial Audio Interface Master Mode Timing
DS648F2
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