CS42448_06 Datasheet, PDF (41/64 Pages) Cirrus Logic – 108 dB, 192 kHz 6-In, 8-Out CODEC

CS42448
6. REGISTER DESCRIPTION
All registers are read/write except for the I.D. and Revision Register and Interrupt Status Register which are read
only. See the following bit-definition tables for bit assignment information. The default state of each bit after a power-
up sequence or reset is listed in each bit description.
6.1 Memory Address Pointer (MAP)
Not a register
7
INCR
6
MAP6
5
MAP5
4
MAP4
3
MAP3
2
MAP2
1
MAP1
0
MAP0
6.1.1
Increment (INCR)
Default = 1
Function:
Memory address pointer auto increment control
0 - MAP is not incremented automatically.
1 - Internal MAP is automatically incremented after each read or write.
6.1.2
Memory Address Pointer (MAP[6:0])
Default = 0000001
Function:
Memory address pointer (MAP). Sets the register address that will be read or written by the control port.
6.2 Chip I.D. and Revision Register (Address 01h) (Read Only)
7
Chip_ID3
6
Chip_ID2
5
Chip_ID1
4
Chip_ID0
3
Rev_ID3
2
Rev_ID2
1
Rev_ID1
0
Rev_ID0
6.2.1
Chip I.D. (CHIP_ID[3:0])
Default = 0000
Function:
I.D. code for the CS42448. Permanently set to 0000.
6.2.2
Chip Revision (REV_ID[3:0])
Default = 0001
Function:
CS42448 revision level. Revision A is coded as 0001.
DS648F2
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