CS42432_07 Datasheet, PDF (45/58 Pages) Cirrus Logic – 108 dB, 192 kHz 4-In, 6-Out TDM CODEC

CS42432
7.9 AOUTX Volume Control (Addresses 08h-0D)
7
6
5
4
3
2
1
0
AOUTx_VOL7 AOUTx_VOL6 AOUTx_VOL5 AOUTx_VOL4 AOUTx_VOL3 AOUTx_VOL2 AOUTx_VOL1 AOUTx_VOL0
7.9.1
Volume Control (AOUTX_VOL[7:0])
Default = 00h
Function:
The AOUTx Volume Control registers allow independent setting of the signal levels in 0.5 dB increments
from 0 dB to -127.5 dB. Volume settings are decoded as shown in Table 6. The volume changes are im-
plemented as dictated by the Soft and Zero Cross bits (DAC_SZC[1:0]). All volume settings less than -
127.5 dB are equivalent to enabling the AOUTx_MUTE bit for the given channel.
Binary Code
00000000
00101000
01010000
01111000
10110100
Volume Setting
0 dB
-20 dB
-40 dB
-60 dB
-90 dB
Table 6. Example AOUT Volume Settings
7.10 DAC Channel Invert (Address 10h)
7
Reserved
6
Reserved
5
INV_AOUT6
4
INV_AOUT5
3
INV_AOUT4
2
INV_AOUT3
1
INV_AOUT2
0
INV_AOUT1
7.10.1 Invert Signal Polarity (INV_AOUTX)
Default = 0
0 - Disabled
1 - Enabled
Function:
When enabled, these bits will invert the signal polarity of their respective channels.
7.11 AINX Volume Control (Address 11h-14h)
7
AINx_VOL7
6
AINx_VOL6
5
AINx_VOL5
4
AINx_VOL4
3
AINx_VOL3
2
AINx_VOL2
1
AINx_VOL1
0
AINx_VOL0
7.11.1 AINX Volume Control (AINX_VOL[7:0])
Default = 00h
Function:
The level of AIN1 - AIN6 can be adjusted in 0.5 dB increments as dictated by the ADC Soft and Zero Cross
bits (ADC_SZC[1:0]) from +24 to -64 dB. Levels are decoded in two’s complement, as shown in Table 7.
DS673F2
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